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* 85xx: Fix the boot window issueDave Liu2008-12-19-8/+8
| | | | | | | | | | | | | | | | | | | | | | If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+2
| | | | | | | | | | | Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic numberKumar Gala2008-10-24-2/+2
| | | | | | | Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala2008-10-18-0/+49
| | | | | | | | Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-24/+24
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Change the temp map to ROM to align addresses to page size.Andrew Klossner2008-07-14-4/+5
| | | | | | | | | | With a page size of BOOKE_PAGESZ_16M, both the real and effective addresses must be multiples of 16MB. The hardware silently truncates them so the code happens to work. This patch clarifies the situation by establishing addresses that the hardware doesn't need to truncate. Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Big white-space cleanup.Wolfgang Denk2008-05-21-1/+1
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Don't icbi when unlocking the cacheKumar Gala2008-02-27-5/+2
| | | | | | | | | There is no reason to icbi when invalidating the temporary stack in the d-cache. Its impossible on e500 to have the i-cache contain any addresses in the temp stack and it can be problematic in generating transactions on the bus to non-valid addresses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Invalidate INIT_RAM TLB mappingsAndy Fleming2008-02-27-0/+11
| | | | | | | | | | | | | | | Commit 0db37dc... (and some others) changed the INIT_RAM TLB mappings to be unguarded. This collided with an existing "bug" where the mappings for the INIT_RAM were being kept around. This meant that speculative loads to those addresses were succeeding in the TLB, and going out to the bus, where they were causing an exception (there's nothing at that address). The Flash code was coincidentally causing such a speculative load. Rather than go back to mapping the INIT RAM as guarded, we fix it so that the entries for the INIT_RAM are invalidated. Thus the speculative loads will fail in the TLB, and have no effect. Signed-off-by: Andy Fleming <afleming@freescale.com>
* ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-45/+0
| | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* 85xx: Reworked initial processor initKumar Gala2008-01-17-68/+63
| | | | | | | | | | | | | | | | | | | Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that. There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove old style of LAW initKumar Gala2008-01-16-18/+0
| | | | | | All boards are now using the new fsl_law code so we can drop the old version. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Move LAW init code into CKumar Gala2008-01-16-0/+2
| | | | | | | | | | | Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-2/+7
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Cleanup coding style; update CHANGELOGWolfgang Denk2007-11-03-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MSR overwrite fixurwithsughosh@gmail.com2007-10-19-8/+3
| | | | | | | | Hello, This patch fixes the MSR overwrite in the start.S when moving out of the last 4K page. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
* Remove magic numbers from cache related operations for mpc85xxKumar Gala2007-10-19-4/+4
| | | | | | | The mpc85xx start code uses some magic numbers that we actually have #defines for in <config.h> so use those instead. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx io out functions need sync after write.Ed Swarthout2007-09-26-0/+5
| | | | | | This fixes the mc146818 rtc_read/write functions for 85xx. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* Use an absolute address when jumping out of 4k boot pageKumar Gala2007-08-14-29/+24
| | | | | | | On e500 when we leave the 4k boot page we should use an absolute address since we don't know where the board code may want us to be really running at. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx start.S cleanup and exception supportAndy Fleming2007-08-14-278/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | From: Ed Swarthout <Ed.Swarthout@freescale.com> Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-2/+2
| | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* u-boot: v2: Remove the fixed TLB and LAW entrynubmerZang Roy-r619112007-04-23-12/+4
| | | | | | | | | Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward <swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* Fix bug in [id]cache_status commands for MPC85xx processors;Wolfgang Denk2006-03-13-2/+2
| | | | | | should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
* Added support for KwikByte KB920x boards (based on AT91RM9200)Wolfgang Denk2005-10-05-1/+1
| | | | Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
* E500 update: repoint IVPR to RAM when code is relocatedWolfgang Denk2005-10-05-0/+5
| | | | Patch by Kylo Ginsberg, 13 Apr 2005
* Merge with /home/wd/git/u-boot/masterWolfgang Denk2005-08-05-2/+2
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| * Fix typos in cpu/85xx/start.S which caused DataTLB exception to beWolfgang Denk2005-08-04-2/+2
| | | | | | | | | | routed to the Watchdog handler Patch by Eugene Surovegin, 18 Jun 2005
* | * Patch by Ron Alder, 11 July 2005Lunsheng Wang2005-07-29-3/+5
| | | | | | | | | | Add Xianghua Xiao and Lunsheng Wang's support for the GDA MPC8540 EVAL board.
* | * Patch by Jon Loeliger, 2005-05-05Jon Loeliger2005-07-25-0/+6
|/ | | | | | | | Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
* Fix timer handling on MPC85xx systemswdenk2005-05-13-164/+144
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* Patch by Jon Loeliger, 16 Jul 2004:wdenk2004-08-01-21/+15
| | | | | | | | | | | | | - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads
* Patch by Jon Loeliger, 17 June 2004:wdenk2004-07-09-29/+17
| | | | | | | | Completion of the 8540ADS/8560ADS updates: Fix some PCI and Rapid I/O memory maps, Initialize both TSEC 1 and 2, Initialize SDRAM Update MAINTAINER for 85xx boards and README.mpc85xxads
* Patches Part 1 by Jon Loeliger, 11 May 2004:wdenk2004-06-09-21/+45
| | | | | | | | | | | | | | | | | | | | | | Dynamically handle REV1 and REV2 MPC85xx parts. (Jon Loeliger, 10-May-2004). New consistent memory map and Local Access Window across MPC85xx line. New CCSRBAR at 0xE000_0000 now. Add RAPID I/O memory map. New memory map in README.MPC85xxads (Kumar Gala, 10-May-2004) Better board and CPU identification on MPC85xx boards at boot. (Jon Loeliger, 10-May-2004) SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. (Jim Robertson, 10-May-2004) Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. Supports multiple PHYs. (Andy Fleming, 10-May-2004) Some README.MPC85xxads updates. (Kumar Gala, 10-May-2004) Copyright updates for "Freescale" (Andy Fleming, 10-May-2004)
* * Patch by Xiao Xianghua, 23 Oct 2003:wdenk2003-10-26-2/+4
| | | | | | | | small patch for mpc85xx * Fix small problem in MPC5200 I2C driver * Fix FCC3 support on ATC board
* * Patches by Xianghua Xiao, 15 Oct 2003:wdenk2003-10-15-0/+1156
- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
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