summaryrefslogtreecommitdiff
path: root/cpu/mpc85xx/start.S
Commit message (Collapse)AuthorAgeLines
* u-boot: v2: Remove the fixed TLB and LAW entrynubmerZang Roy-r619112007-04-23-12/+4
| | | | | | | | | Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward <swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* Fix bug in [id]cache_status commands for MPC85xx processors;Wolfgang Denk2006-03-13-2/+2
| | | | | | should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
* Added support for KwikByte KB920x boards (based on AT91RM9200)Wolfgang Denk2005-10-05-1/+1
| | | | Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
* E500 update: repoint IVPR to RAM when code is relocatedWolfgang Denk2005-10-05-0/+5
| | | | Patch by Kylo Ginsberg, 13 Apr 2005
* Merge with /home/wd/git/u-boot/masterWolfgang Denk2005-08-05-2/+2
|\
| * Fix typos in cpu/85xx/start.S which caused DataTLB exception to beWolfgang Denk2005-08-04-2/+2
| | | | | | | | | | routed to the Watchdog handler Patch by Eugene Surovegin, 18 Jun 2005
* | * Patch by Ron Alder, 11 July 2005Lunsheng Wang2005-07-29-3/+5
| | | | | | | | | | Add Xianghua Xiao and Lunsheng Wang's support for the GDA MPC8540 EVAL board.
* | * Patch by Jon Loeliger, 2005-05-05Jon Loeliger2005-07-25-0/+6
|/ | | | | | | | Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
* Fix timer handling on MPC85xx systemswdenk2005-05-13-164/+144
|
* Patch by Jon Loeliger, 16 Jul 2004:wdenk2004-08-01-21/+15
| | | | | | | | | | | | | - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads
* Patch by Jon Loeliger, 17 June 2004:wdenk2004-07-09-29/+17
| | | | | | | | Completion of the 8540ADS/8560ADS updates: Fix some PCI and Rapid I/O memory maps, Initialize both TSEC 1 and 2, Initialize SDRAM Update MAINTAINER for 85xx boards and README.mpc85xxads
* Patches Part 1 by Jon Loeliger, 11 May 2004:wdenk2004-06-09-21/+45
| | | | | | | | | | | | | | | | | | | | | | Dynamically handle REV1 and REV2 MPC85xx parts. (Jon Loeliger, 10-May-2004). New consistent memory map and Local Access Window across MPC85xx line. New CCSRBAR at 0xE000_0000 now. Add RAPID I/O memory map. New memory map in README.MPC85xxads (Kumar Gala, 10-May-2004) Better board and CPU identification on MPC85xx boards at boot. (Jon Loeliger, 10-May-2004) SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. (Jim Robertson, 10-May-2004) Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. Supports multiple PHYs. (Andy Fleming, 10-May-2004) Some README.MPC85xxads updates. (Kumar Gala, 10-May-2004) Copyright updates for "Freescale" (Andy Fleming, 10-May-2004)
* * Patch by Xiao Xianghua, 23 Oct 2003:wdenk2003-10-26-2/+4
| | | | | | | | small patch for mpc85xx * Fix small problem in MPC5200 I2C driver * Fix FCC3 support on ATC board
* * Patches by Xianghua Xiao, 15 Oct 2003:wdenk2003-10-15-0/+1156
- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
generated by cgit v1.1 at 2024-11-15 01:26:55 +0000