summaryrefslogtreecommitdiff
path: root/cpu/mpc85xx/spd_sdram.c
Commit message (Collapse)AuthorAgeLines
* 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docsKumar Gala2008-04-29-2/+2
| | | | | | | All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use SVR_SOC_VER instead of SVR_VERKumar Gala2008-04-11-1/+1
| | | | | | | | The recent change introduced by 'Update SVR numbers to expand support' now requires that we use SVR_SOC_VER instead of SVR_VER if we want to compare against a particular processor id. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Introduce new tlb APIKumar Gala2008-01-17-13/+3
| | | | | | | | | | Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove old style of LAW initKumar Gala2008-01-16-10/+0
| | | | | | All boards are now using the new fsl_law code so we can drop the old version. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Move LAW init code into CKumar Gala2008-01-16-0/+8
| | | | | | | | | | | Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Reworked FSL Book-E TLB macros to be more readableKumar Gala2008-01-09-13/+10
| | | | | | | | | | | The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Handle Asynchronous DDR clock on 85xxKumar Gala2007-12-11-3/+3
| | | | | | | | | | The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t on 85xxKumar Gala2007-12-11-6/+3
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t for guts offset on 85xxKumar Gala2007-12-11-1/+1
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Empirically set cpo and clk_adjust for mpc85xx DDR2 supportHaiying Wang2007-08-14-5/+7
| | | | | | | | | | | | | | This patch is against u-boot-mpc85xx.git of www.denx.com Setting cpo to 0x9 for frequencies higher than 333MHz is verified on both MPC8548CDS board and MPC8568MDS board, especially for supporting 533MHz DDR2. Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for DDR2 on all current board versions especially ver 1.92 or later to bring up. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* MPC85xx BA bits not set for 3-bit bank address DIMMAndy Fleming2007-08-14-1/+6
| | | | | | | | | | The current implementation does not set the number of bank address bits (BA) in the processor. The default assumes 2 logical bank bits. This works fine for a DIMM that uses devices with 4 internal banks (SPD byte17 = 0x4) but needs to be set appropriately for a DIMM that uses devices with 8 internal banks (SPD byte17 = 0x8). Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
* 85xx allow debugger to configure ddr.Ed Swarthout2007-08-14-3/+45
| | | | | | | Only check for mpc8548 rev 1 when compiled for 8548. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Support 1G size on 8548Andy Fleming2007-04-23-2/+9
| | | | | | | e500v2 and newer cores support 1G page sizes. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Only set ddrioovcr for 8548 rev1.Andy Fleming2007-04-23-6/+7
| | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Tweak DDR ECC error counterAndy Fleming2007-04-23-2/+5
| | | | | | | Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Code cleanupWolfgang Denk2006-10-24-1/+1
|
* Coding style changes to remove local varible blocksJon Loeliger2006-10-10-70/+64
| | | | and reformat a bit nicer.
* Fix style issues primarily in 85xx and 83xx boards.Jon Loeliger2005-08-01-2/+2
| | | | | | | | - C++ comments - Trailing white space - Indentation not by TAB - Excessive amount of empty lines - Trailing empty lines
* * Patch by Jon Loeliger, 2005-05-05Jon Loeliger2005-07-25-219/+877
| | | | | | | | Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
* Patches by Josef Wagner, 29 Oct 2004:wdenk2005-04-03-11/+3
| | | | | - Add support for MicroSys CPU87 board - Add support for MicroSys PM854 board
* Patch by Jon Loeliger, 16 Jul 2004:wdenk2004-08-01-139/+263
| | | | | | | | | | | | | - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads
* Patches Part 1 by Jon Loeliger, 11 May 2004:wdenk2004-06-09-140/+176
| | | | | | | | | | | | | | | | | | | | | | Dynamically handle REV1 and REV2 MPC85xx parts. (Jon Loeliger, 10-May-2004). New consistent memory map and Local Access Window across MPC85xx line. New CCSRBAR at 0xE000_0000 now. Add RAPID I/O memory map. New memory map in README.MPC85xxads (Kumar Gala, 10-May-2004) Better board and CPU identification on MPC85xx boards at boot. (Jon Loeliger, 10-May-2004) SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. (Jim Robertson, 10-May-2004) Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. Supports multiple PHYs. (Andy Fleming, 10-May-2004) Some README.MPC85xxads updates. (Kumar Gala, 10-May-2004) Copyright updates for "Freescale" (Andy Fleming, 10-May-2004)
* * Patches by Xianghua Xiao, 15 Oct 2003:wdenk2003-10-15-0/+308
- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
generated by cgit v1.1 at 2024-12-18 05:37:37 +0000