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* Enable backside L2
* e500mc no longer has timebase enable in HID (moved to CCSR register)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.
* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The e500um says the timebase is volatile out of reset. To ensure
TB sync works we need to make sure its zero.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Use CONFIG_NUM_CPUS to match existing define used by 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
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* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up. This fixes an issue if
the "boot cpu" isn't core0. The "boot cpu" will already be in the
cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior. These
changes are explicitly needed but don't hurt:
- Added eieio to ensure the "hot word" of the table is written after
all other table updates have occurred.
- Added isync to ensure we don't prefetch loading of table entries
until we a released
These issues we raised by Dave Liu.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The following changes are needed to be inline with ePAPR v0.81:
* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.
Added support for using the ePAPR defined spin-table mechanism on 85xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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