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* mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-1/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t on 85xxKumar Gala2007-12-11-3/+2
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdtKumar Gala2007-12-11-27/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t for guts offset on 85xxKumar Gala2007-12-11-1/+1
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xxCDS: Add make targets for legacy systems.Randy Vinson2007-08-14-1/+1
| | | | | | | | The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson <rvinson@mvista.com>
* Cleaned up some 85xx PCI bugsAndy Fleming2007-05-02-4/+4
| | | | | | | | | | | * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming <afleming@freescale.com>
* * Fix a bunch of compiler warnings for gcc 4.0Matthew McClintock2006-10-11-0/+5
| | | | Signed-off-by: Matthew McClintock <msm@freescale.com>
* * Switched default PCI speed for 8540 ADS back to 33MHzMatthew McClintock2006-06-28-0/+3
| | | | | | | | * Added comments and a printf to warn that PCI-X won't work at 33MHz Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* * Added support for initializing second PCI bus on 85xxMatthew McClintock2006-06-28-35/+147
| | | | | | Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix MPC85xx PCI support (pci_register_hose() before pci config access)Stefan Roese2005-11-07-10/+10
| | | | Patch by Stefan Roese, 07 Nov 2005
* Patches by Scott McNutt, 24 Aug 2004:wdenk2004-10-10-1/+0
| | | | | | - Add support for Altera Nios-II processors. - Add support for Psyent PCI-5441 board. - Add support for Psyent PK1C20 board.
* * Patch by Jon Loeliger, 24 Aug 2004:wdenk2004-10-10-2/+28
| | | | | | | | | | | - Fix PCI window on MPC85xx; remove unneeded PCI initialization from board_early_init_f() - Provide SW workaround for PCI initialization on 85xx CDS - Convert MPC85xxADS to use common CFI flash driver * Cleanup: avoid compiler warnings * Add CMC PU2 board to MAKEALL script
* Patch by Jon Loeliger, 16 Jul 2004:wdenk2004-08-01-48/+30
| | | | | | | | | | | | | - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads
* Patch by Jon Loeliger, 17 June 2004:wdenk2004-07-09-59/+67
| | | | | | | | Completion of the 8540ADS/8560ADS updates: Fix some PCI and Rapid I/O memory maps, Initialize both TSEC 1 and 2, Initialize SDRAM Update MAINTAINER for 85xx boards and README.mpc85xxads
* * Patches by Xianghua Xiao, 15 Oct 2003:wdenk2003-10-15-0/+107
- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
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