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* 8xxx: Move dma_init() call to common codePeter Tyser2009-07-01-1/+3
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for additional e500mc featuresKumar Gala2009-03-30-0/+13
| | | | | | | * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: init gd as early as possibleKumar Gala2008-12-04-6/+6
| | | | | | | | Moved up the initialization of GD so C code like set_tlb() can use gd->flags to determine if we've relocated or not in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Fix relocation of CCSRBARKumar Gala2008-12-04-4/+5
| | | | | | | | | | If the virtual address for CCSRBAR is the same after relocation but the physical address is changing we'd end up having two TLB entries with the same VA. Instead we new us the new CCSRBAR virt address + 4k as a temp virt address to access the old CCSRBAR to relocate it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add CPU 2 errata workaround to all 8548 boardsPeter Tyser2008-12-03-0/+13
| | | | | | | | | | | All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-44/+44
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-0/+7
| | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
* 85xx: Cleanup L2 cache size detectionKumar Gala2008-07-14-17/+30
| | | | | | | | | | The L2 size detection code was a bit confusing and we kept having to add code to it to handle new processors. Change the sense of detection so we look for the older processors that aren't changing. Also added support for 1M cache size on 8572. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL LAW: Keep track of LAW allocationsKumar Gala2008-06-11-17/+6
| | | | | | | | | | | | | | | Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* MPC85xx: Beautify boot output of L2 cache configurationWolfgang Grandegger2008-06-10-8/+10
| | | | | | | | | | The boot output is now aligned poperly with other boot output lines, e.g.: FLASH: 128 MB L2: 512 KB enabled Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* 85xx: Use SVR_SOC_VER instead of SVR_VERKumar Gala2008-04-11-1/+1
| | | | | | | | The recent change introduced by 'Update SVR numbers to expand support' now requires that we use SVR_SOC_VER instead of SVR_VER if we want to compare against a particular processor id. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+4
| | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-3/+3
| | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Get ride of old TLB setup codeKumar Gala2008-01-17-20/+0
| | | | | | | Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Reworked initial processor initKumar Gala2008-01-17-4/+52
| | | | | | | | | | | | | | | | | | | Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that. There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Move LAW init code into CKumar Gala2008-01-16-0/+8
| | | | | | | | | | | Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t on 85xxKumar Gala2007-12-11-7/+3
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t for cpm offset on 85xxKumar Gala2007-12-11-3/+3
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Enable L2 cache for MPC8568MDS boardHaiying Wang2007-08-29-1/+1
| | | | | | The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Add support for UEC to 8568Andy Fleming2007-08-14-0/+33
| | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix minor 85xx warningsAndy Fleming2007-08-14-1/+3
| | | | | | | | | | | Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming <afleming@freescale.com>
* mpc85xx L2 cache reporting and SRAM relocation option.Ed Swarthout2007-08-14-18/+47
| | | | | | | | Allow debugger to override flash cs0/cs1 settings to enable alternate boot regions Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Add support for the 8568 MDS boardAndy Fleming2007-05-02-2/+0
| | | | | | | | | This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming <afleming@freescale.com>
* * Add Flat Dev Tree construction for MPC85xx ADS and CDS boardsMatthew McClintock2006-06-28-0/+1
| | | | | | Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger <jdl@freescale.com>
* GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-1/+2
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* * Patch by Jon Loeliger, 2005-05-05Jon Loeliger2005-07-25-13/+29
| | | | | | | | Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
* * Patch by Jon Loeliger 2005-02-08Jon Loeliger2005-07-25-1/+16
| | | | Determine L2 Cache size dynamically on 85XX boards.
* * Patch by Jon Loeliger, Kumar Gala 2005-02-08Jon Loeliger2005-07-23-3/+3
| | | | | | | | - Convert the CPM2 based functionality to use new CONFIG_CPM2 option rather than a myriad of CONFIG_MPC8560-like variants. Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. Eliminates the CONFIG_MPC8560 option entirely. Distributes the new CONFIG_CPM2 option to each 8260 board.
* Update code for TQM8540 board (and 85xx in general):wdenk2005-03-15-2/+2
| | | | | | | - Change the name of the Ethernet driver: MOTO ENET -> ENET - Reformat boot messages - Enable redundant environment - Replace the -O2 optimization flag with -mno-string
* * Patches by Xianghua Xiao, 15 Oct 2003:wdenk2003-10-15-0/+205
- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
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