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* NAND boot: MPC8313ERDB supportScott Wood2008-08-12-107/+157
| | | | | | | | | Note that with older board revisions, NAND boot may only work after a power-on reset, and not after a warm reset. I don't have a newer board to test on; if you have a board with a 33MHz crystal, please let me know if it works after a warm reset. Signed-off-by: Scott Wood <scottwood@freescale.com>
* 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreqPaul Gortmaker2008-07-14-1/+1
| | | | | | | | | | Some boards that have external 16550 UARTs don't have a direct tie between bi_busfreq and the clock used for the UARTs. Boards that do have such a tie should set CFG_NS16550_CLK to be get_bus_freq(0) -- which most of them do already. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* fdt: add crypto node handling for MPC8{3, 5}xxE processorsKim Phillips2008-07-14-0/+18
| | | | | | | | Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* silence misc printf formatting compiler warningsKim Phillips2008-07-10-4/+4
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-netWolfgang Denk2008-07-09-0/+20
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| * Add mechanisms for CPU and board-specific Ethernet initializationBen Warren2008-07-06-0/+20
| | | | | | | | | | | | | | | | This patch is the first step in cleaning up net/eth.c, by moving Ethernet initialization to CPU or board-specific code. Initial implementation is only on the Freescale TSEC controller, but others will be added soon. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | fix system config overwrite @ MPC834x and MPC8313Andre Schwarz2008-06-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During 83xx setup the "System I/O configuration register high" gets overwritten with user defined value if CFG_SICRH is defined. Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH must keep their reset value regardless of configuration. On my board (using RGMII) those bits are set after reset - yet it's unclear where they come from. The patch keeps both bits on MPC834x and MPC8313. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: move CPU_TYPE_ENTRY over to processor.hKim Phillips2008-06-25-1/+0
|/ | | | | | | | | | to avoid this: cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined In file included from cpu.c:33: /home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* PPC: Create and use CONFIG_HIGH_BATSBecky Bruce2008-06-03-3/+3
| | | | | | | | | | | Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Big white-space cleanup.Wolfgang Denk2008-05-21-6/+6
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc83xx: remove the unused CPM's stuffDave Liu2008-04-25-8/+0
| | | | | | The MPC83xx family never have CPM block, so remove it from 83xx. Signed-off-by: Dave Liu <daveliu@freescale.com>
* lib_ppc: Revert "Make MPC83xx one step closer to full relocation."Kim Phillips2008-04-25-7/+4
| | | | | | | | This reverts commit 70431e8a7393b6b793f77957f95b999fc9a269b8 which has proven problematic getting right from the start at least on 83xx and 4xx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Update DIMM data bus width test to support 40-bit widthLee Nipper2008-04-11-2/+2
| | | | | | | | 32-bit wide ECC memory modules report 40-bit width. Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Make MPC83xx one step closer to full relocation.Joakim Tjernlund2008-03-28-4/+7
| | | | | | | | Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx and use GOT relative reference. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) codeKim Phillips2008-03-28-123/+43
| | | | | | | | | | in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6, 85xx's "Update SVR numbers to expand support", simplify SPRIDR processing and processor ID display. Add REVID_{MAJ,MIN}OR macros to make REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR convenience macros. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: display ddr frequency in board_add_ram_info bannerKim Phillips2008-03-28-4/+7
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: unreinvent mem_clkKim Phillips2008-03-28-13/+13
| | | | | | | delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to mem_*_clk for consistency's sake. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixupsAnton Vorontsov2008-03-25-0/+8
| | | | | | | | | | device_type = "soc" is being deprecated, newer device trees will use "fsl,soc" and/or "fsl,immr" for the soc nodes. This patch also adds clock-frequency property for soc nodes (the same value as bus-frequency). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: serdes setup routinesAnton Vorontsov2008-03-25-0/+146
| | | | | | This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: split COBJS onto separate linesAnton Vorontsov2008-03-25-11/+12
| | | | | | ..plus get rid of some #ifdefs in the .c files. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* mpc8323erdb: Improve the system performanceMichael Barkowski2008-03-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* PPC: Use r2 instead of r29 as global data pointerWolfgang Denk2008-02-14-1/+1
| | | | | | | | | | | | R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc will refuse to use load/store multiple insns; instead, it issues a list of simple load/store instructions upon function entry and exit, resulting in bigger code size, which in turn makes the build for a few boards fail. Use r2 instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-34/+0
| | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* QE: Move FDT support into a common fileKumar Gala2008-02-12-10/+3
| | | | | | | Move the flat device tree setup for QE related devices into a common file shared between 83xx & 85xx platforms that have QE's. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: Fix the fatal conflict of mergeDave Liu2008-01-17-11/+6
| | | | | | | | | | | | The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 will cause the mpc8315erdb board can't boot up. The patch fix that bug, and remove the duplicated #ifdef CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for MPC8313E processor. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add support for more system clock performance controlsKim Phillips2008-01-16-28/+57
| | | | | | | | | | System registers that are modified are the Arbiter Configuration Register (ACR), the System Priority Control Register (SPCR), and the System Clock Configuration Register (SCCR). Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com> Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add config of eTSEC emergency priority in SPCRDave Liu2008-01-16-0/+5
| | | | | | | | | | | The TSEC emergency priority definition of 831x/837x is different than the definition of 834x in SPCR register. Add the other config of TSEC emergency priority into cpu_init.c Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-12-1/+1
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fixed syntax error in function init_e300_core() of mpc83xx/start.S ifHeiko Schocher2008-01-12-1/+1
| | | | | Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc83xx: Fix the bug of 266MHz data rate DDRDave Liu2008-01-10-3/+3
| | | | | | | | The DDR doesn't work on the 266MHz data rate, the patch fix the bug. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add "fsl, qe" compatible fixupsAnton Vorontsov2008-01-10-0/+6
| | | | | | | New device trees will use "fsl,qe" compatible properties. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: convert to using do_fixup_*()Kim Phillips2008-01-08-480/+103
| | | | | | | | | convert to using simpler mpc85xx style fdt update code; streamline by eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm the old school FLAT_TREE code from 83xx (since the sbc8349 was just converted over to using libfdt). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add support CONFIG_UEC_ETH3 in MPC83xxJoakim Tjernlund2008-01-08-1/+115
| | | | Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* mpc83xx: Add the support of MPC837xEMDS boardDave Liu2008-01-08-3/+10
| | | | | | | | | | | The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Add the support of MPC8315E SoCDave Liu2008-01-08-3/+49
| | | | | | | The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Add the support of MPC837x SoCDave Liu2008-01-08-30/+161
| | | | | | | The MPC837x SoC including e300c4 core and new IP blocks, such as SDHC, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Convert boards that set memory node to use fdt_fixup_memory()Kumar Gala2007-12-07-16/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update libfdt from device tree compiler (dtc)Kumar Gala2007-11-21-4/+4
| | | | | | | Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from the device tree compiler (dtc) project. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "Correct fixup relocation for mpc83xx"Grant Likely2007-11-15-1/+2
| | | | | This reverts commit 057004f4a4863554d56cc56268bfa7c7d9738e27. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* mpc83xx: fix typo in DDR2 programmingKim Phillips2007-08-17-1/+1
| | | | | | | introduced in the implement board_add_ram_info patch as I was cleaning out the magic numbers. sorry. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: implement board_add_ram_infoKim Phillips2007-08-16-15/+39
| | | | | | | | | | | | | | | | add board_add_ram_info, to make memory diagnostic output more consistent. u-boot banner output now looks like: DRAM: 256 MB (DDR1, 64-bit, ECC on) and for boards with SDRAM on the local bus, a line such as this is added: SDRAM: 64 MB (local bus) also replaced some magic numbers with their equivalent define names. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: migrate remaining freescale boards to libfdtKim Phillips2007-08-15-3/+12
| | | | | | | | | | this adds libfdt support code for the freescale mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx, and gp boards. Boards remain compatible with OF_FLAT_TREE. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: move common /memory node update mechanism to cpu.cKim Phillips2007-08-15-8/+23
| | | | | | also adds common prototypes to include/common.h. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: remaining 8360 libfdt fixesKim Phillips2007-08-15-20/+47
| | | | | | | | | | PCI clocks and QE frequencies weren't being updated, and the core clock was being updated incorrectly. This patch also adds a /memory node if it doesn't already exist prior to update. plus some cosmetic trimming to single line comments. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix UEC2->1 typo in libfdt setup codeKim Phillips2007-08-15-1/+1
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Suppress the warning 'burstlen'Dave Liu2007-08-10-1/+1
| | | | | | suppress the warning 'burstlen' of spd_sdram. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Consolidate the ECC support of 83xxDave Liu2007-08-10-1/+391
| | | | | | | | Remove the duplicated source code of ecc command on the <board>.c, for reused, move these code to cpu/mpc83xx directory. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Correct the burst length for DDR2 with 32 bitsDave Liu2007-08-10-3/+10
| | | | | | The burst length should be 4 for DDR2 with 32 bits bus Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: fixup generic pci for libfdtKim Phillips2007-08-10-1/+35
| | | | | | add libfdt support to the generic 83xx pci code Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix 8360 and cpu functions to update fdt being passedKim Phillips2007-08-10-18/+18
| | | | | | | ..and not the global fdt. Rename local fdt vars to blob so as not to be confused with the global var with the same three-letter name. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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