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* Make MPC83xx one step closer to full relocation.Joakim Tjernlund2008-03-28-4/+7
| | | | | | | | Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx and use GOT relative reference. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) codeKim Phillips2008-03-28-123/+43
| | | | | | | | | | in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6, 85xx's "Update SVR numbers to expand support", simplify SPRIDR processing and processor ID display. Add REVID_{MAJ,MIN}OR macros to make REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR convenience macros. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: display ddr frequency in board_add_ram_info bannerKim Phillips2008-03-28-4/+7
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: unreinvent mem_clkKim Phillips2008-03-28-13/+13
| | | | | | | delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to mem_*_clk for consistency's sake. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixupsAnton Vorontsov2008-03-25-0/+8
| | | | | | | | | | device_type = "soc" is being deprecated, newer device trees will use "fsl,soc" and/or "fsl,immr" for the soc nodes. This patch also adds clock-frequency property for soc nodes (the same value as bus-frequency). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: serdes setup routinesAnton Vorontsov2008-03-25-0/+146
| | | | | | This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: split COBJS onto separate linesAnton Vorontsov2008-03-25-11/+12
| | | | | | ..plus get rid of some #ifdefs in the .c files. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* mpc8323erdb: Improve the system performanceMichael Barkowski2008-03-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* PPC: Use r2 instead of r29 as global data pointerWolfgang Denk2008-02-14-1/+1
| | | | | | | | | | | | R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc will refuse to use load/store multiple insns; instead, it issues a list of simple load/store instructions upon function entry and exit, resulting in bigger code size, which in turn makes the build for a few boards fail. Use r2 instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-34/+0
| | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* QE: Move FDT support into a common fileKumar Gala2008-02-12-10/+3
| | | | | | | Move the flat device tree setup for QE related devices into a common file shared between 83xx & 85xx platforms that have QE's. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: Fix the fatal conflict of mergeDave Liu2008-01-17-11/+6
| | | | | | | | | | | | The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 will cause the mpc8315erdb board can't boot up. The patch fix that bug, and remove the duplicated #ifdef CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for MPC8313E processor. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add support for more system clock performance controlsKim Phillips2008-01-16-28/+57
| | | | | | | | | | System registers that are modified are the Arbiter Configuration Register (ACR), the System Priority Control Register (SPCR), and the System Clock Configuration Register (SCCR). Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com> Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add config of eTSEC emergency priority in SPCRDave Liu2008-01-16-0/+5
| | | | | | | | | | | The TSEC emergency priority definition of 831x/837x is different than the definition of 834x in SPCR register. Add the other config of TSEC emergency priority into cpu_init.c Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-12-1/+1
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fixed syntax error in function init_e300_core() of mpc83xx/start.S ifHeiko Schocher2008-01-12-1/+1
| | | | | Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc83xx: Fix the bug of 266MHz data rate DDRDave Liu2008-01-10-3/+3
| | | | | | | | The DDR doesn't work on the 266MHz data rate, the patch fix the bug. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add "fsl, qe" compatible fixupsAnton Vorontsov2008-01-10-0/+6
| | | | | | | New device trees will use "fsl,qe" compatible properties. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: convert to using do_fixup_*()Kim Phillips2008-01-08-480/+103
| | | | | | | | | convert to using simpler mpc85xx style fdt update code; streamline by eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm the old school FLAT_TREE code from 83xx (since the sbc8349 was just converted over to using libfdt). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add support CONFIG_UEC_ETH3 in MPC83xxJoakim Tjernlund2008-01-08-1/+115
| | | | Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* mpc83xx: Add the support of MPC837xEMDS boardDave Liu2008-01-08-3/+10
| | | | | | | | | | | The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Add the support of MPC8315E SoCDave Liu2008-01-08-3/+49
| | | | | | | The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Add the support of MPC837x SoCDave Liu2008-01-08-30/+161
| | | | | | | The MPC837x SoC including e300c4 core and new IP blocks, such as SDHC, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Convert boards that set memory node to use fdt_fixup_memory()Kumar Gala2007-12-07-16/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update libfdt from device tree compiler (dtc)Kumar Gala2007-11-21-4/+4
| | | | | | | Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from the device tree compiler (dtc) project. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "Correct fixup relocation for mpc83xx"Grant Likely2007-11-15-1/+2
| | | | | This reverts commit 057004f4a4863554d56cc56268bfa7c7d9738e27. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* mpc83xx: fix typo in DDR2 programmingKim Phillips2007-08-17-1/+1
| | | | | | | introduced in the implement board_add_ram_info patch as I was cleaning out the magic numbers. sorry. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: implement board_add_ram_infoKim Phillips2007-08-16-15/+39
| | | | | | | | | | | | | | | | add board_add_ram_info, to make memory diagnostic output more consistent. u-boot banner output now looks like: DRAM: 256 MB (DDR1, 64-bit, ECC on) and for boards with SDRAM on the local bus, a line such as this is added: SDRAM: 64 MB (local bus) also replaced some magic numbers with their equivalent define names. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: migrate remaining freescale boards to libfdtKim Phillips2007-08-15-3/+12
| | | | | | | | | | this adds libfdt support code for the freescale mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx, and gp boards. Boards remain compatible with OF_FLAT_TREE. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: move common /memory node update mechanism to cpu.cKim Phillips2007-08-15-8/+23
| | | | | | also adds common prototypes to include/common.h. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: remaining 8360 libfdt fixesKim Phillips2007-08-15-20/+47
| | | | | | | | | | PCI clocks and QE frequencies weren't being updated, and the core clock was being updated incorrectly. This patch also adds a /memory node if it doesn't already exist prior to update. plus some cosmetic trimming to single line comments. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix UEC2->1 typo in libfdt setup codeKim Phillips2007-08-15-1/+1
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Suppress the warning 'burstlen'Dave Liu2007-08-10-1/+1
| | | | | | suppress the warning 'burstlen' of spd_sdram. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Consolidate the ECC support of 83xxDave Liu2007-08-10-1/+391
| | | | | | | | Remove the duplicated source code of ecc command on the <board>.c, for reused, move these code to cpu/mpc83xx directory. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Correct the burst length for DDR2 with 32 bitsDave Liu2007-08-10-3/+10
| | | | | | The burst length should be 4 for DDR2 with 32 bits bus Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: fixup generic pci for libfdtKim Phillips2007-08-10-1/+35
| | | | | | add libfdt support to the generic 83xx pci code Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix 8360 and cpu functions to update fdt being passedKim Phillips2007-08-10-18/+18
| | | | | | | ..and not the global fdt. Rename local fdt vars to blob so as not to be confused with the global var with the same three-letter name. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Fix errors when CONFIG_OF_LIBFDT is enabledJerry Van Baren2007-08-10-28/+46
| | | | | | | | | | Several node strings were not correct (trailing slashes and properties in the strings) Added setting of the timebase-frequency. Improved error messages and use debug() instead of printf(). Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path().Jerry Van Baren2007-08-10-6/+3
| | | | | | | | | | | The new name matches more closely the kernel's name, which is also a much better description. These are the mpc83xx changes made necessary by the function name change. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add support for the display of reset statusDave Liu2007-08-10-0/+36
| | | | | | | | | | | | | 83xx processor family has many reset sources, such as power on reset, software hard reset, software soft reset, JTAG, bus monitor, software watchdog, check stop reset, external hard reset, external software reset. sometimes, to figure out the fault of system, we need to know the cause of reset early before the prompt of u-boot present. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Update SCCR programming in cpu_init_f() to support all 83xx processorsTimur Tabi2007-08-10-2/+12
| | | | | | | | | | | | | Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the bitfields for all 83xx processors. The code to update some bitfields was compiled only on some processors. Now, the bitfields are programmed as long as the corresponding CFG_SCCR option is defined in the board header file. This means that the board header file should not define any CFG_SCCR macros for bitfields that don't exist on that processor, otherwise the SCCR will be programmed incorrectly. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add support for 8360 silicon revision 2.1Lee Nipper2007-08-10-1/+4
| | | | | | | This change adds 8360 silicon revision 2.1 support to u-boot. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* cpu/m*: Remove obsolete references to CONFIG_COMMANDSJon Loeliger2007-07-09-9/+9
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Correct fixup relocation for mpc83xxGrant Likely2007-07-04-2/+1
| | | | Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* Consolidate mpc83xx linker scriptsGrant Likely2007-07-04-0/+126
| | | | Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*).Jon Loeliger2007-07-04-8/+8
| | | | | | | | | | | | | | This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Merge with /home/wd/git/u-boot/custodian/u-boot-testingWolfgang Denk2007-07-03-4/+4
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| * Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECxKim Phillips2007-05-17-4/+4
| | | | | | | | | | | | | | For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-2/+2
|/ | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* Fix memory initialization on MPC8349E-mITXTimur Tabi2007-05-01-5/+0
| | | | | | | | | | | | | Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Michael Benedict <MBenedict@twacs.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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