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* 83xx: Use the proper sequence for updating IMMR.Scott Wood2009-01-21-3/+15
| | | | | | | | | | | This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Size optimization of start.SRon Madrid2009-01-21-38/+39
| | | | | | | | | | | Currently there are in excess of 100 bytes located at the beginning of the image built by start.S that are not being utilized. This patch moves a few functions into this part of the image. This will create a greater number of *available* bytes that can be used by board specific code in NAND builds and will decrease the size of the assembled code in other builds. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Merge 'next' branchWolfgang Denk2008-10-18-123/+123
|\ | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-123/+123
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | 83xx NAND boot: wait for LTESR[CC]Lepcha Suchit2008-10-17-0/+12
|/ | | | | | | | | | | | At least some revisions of the 8313, and possibly other chips, do not wait for all pages of the initial 4K NAND region to be loaded before beginning execution; thus, we wait for it before branching out of the first NAND page. This fixes warm reset problems when booting from NAND on 8313erdb. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: clean up cache operations and unlock_ram_in_cache() functionsNick Spence2008-09-03-21/+30
| | | | | | | | | Cleans up some latent issues with the data cache control so that dcache_enable() and dcache_disable() will work reliably (after unlock_ram_in_cache() has been called) Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Store and display Arbiter Event Register valuesNick Spence2008-09-03-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheNick Spence2008-09-03-4/+5
| | | | | | | | | | | This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* NAND boot: MPC8313ERDB supportScott Wood2008-08-12-107/+45
| | | | | | | | | Note that with older board revisions, NAND boot may only work after a power-on reset, and not after a warm reset. I don't have a newer board to test on; if you have a board with a 33MHz crystal, please let me know if it works after a warm reset. Signed-off-by: Scott Wood <scottwood@freescale.com>
* PPC: Create and use CONFIG_HIGH_BATSBecky Bruce2008-06-03-3/+3
| | | | | | | | | | | Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* lib_ppc: Revert "Make MPC83xx one step closer to full relocation."Kim Phillips2008-04-25-7/+4
| | | | | | | | This reverts commit 70431e8a7393b6b793f77957f95b999fc9a269b8 which has proven problematic getting right from the start at least on 83xx and 4xx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Make MPC83xx one step closer to full relocation.Joakim Tjernlund2008-03-28-4/+7
| | | | | | | | Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx and use GOT relative reference. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-34/+0
| | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* Fixed syntax error in function init_e300_core() of mpc83xx/start.S ifHeiko Schocher2008-01-12-1/+1
| | | | | Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Heiko Schocher <hs@denx.de>
* [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-2/+2
| | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* mpc83xx: Put the version (and magic) after the HRCW.Jerry Van Baren2007-03-02-12/+16
| | | | | | | Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
* mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-8/+8
| | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Fix the incorrect dcbz operationDave Liu2006-11-03-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 834x rev1.x silicon has one CPU5 errata. The issue is when the data cache locked with HID0[DLOCK], the dcbz instruction looks like no-op inst. The right behavior of the data cache is when the data cache Locked with HID0[DLOCK], the dcbz instruction allocates new tags in cache. The 834x rev3.0 and later and 8360 have not this bug inside. So, when 834x rev3.0/8360 are working with ECC, the dcbz instruction will corrupt the stack in cache, the processor will checkstop reset. However, the 834x rev1.x can work with ECC with these code, because the sillicon has this cache bug. The dcbz will not corrupt the stack in cache. Really, it is the fault code running on fault sillicon. This patch fix the incorrect dcbz operation. Instead of CPU FP writing to initialise the ECC. CHANGELOG: * Fix the incorrect dcbz operation instead of CPU FP writing to initialise the ECC memory. Otherwise, it will corrupt the stack in cache, The processor will checkstop reset. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Add support for variable flash memory sizes on 83xx systemsTimur Tabi2006-11-03-8/+21
| | | | | | | | | CHANGELOG: * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access window registers, instead of using a hard-coded value of 8MB. Signed-off-by: Timur Tabi <timur@freescale.com>
* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.Marian Balakowicz2006-03-14-0/+34
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* Correct shift offsets in icache_status and dcache_status for MPC83xx.Marian Balakowicz2006-03-14-2/+2
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* Enable address translation on MPC83xxKumar Gala2006-02-10-179/+298
| | | | Patch by Kumar Gala, 10 Feb 2006
* Only disable the MPC83xx watchdog if its enabled out of reset.Kumar Gala2006-01-11-0/+6
| | | | | If its disabled out of reset SW can later enable it if so desired Patch by Kumar Gala, 11 Jan 2006
* Fix style issues primarily in 85xx and 83xx boards.Jon Loeliger2005-08-01-41/+38
| | | | | | | | - C++ comments - Trailing white space - Indentation not by TAB - Excessive amount of empty lines - Trailing empty lines
* * Patch by Eran LibertyEran Liberty2005-07-28-0/+1096
Add support for the Freescale MPC8349ADS board.
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