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* ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-34/+0
| | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* Fixed syntax error in function init_e300_core() of mpc83xx/start.S ifHeiko Schocher2008-01-12-1/+1
| | | | | Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Heiko Schocher <hs@denx.de>
* [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-2/+2
| | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* mpc83xx: Put the version (and magic) after the HRCW.Jerry Van Baren2007-03-02-12/+16
| | | | | | | Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
* mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-8/+8
| | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Fix the incorrect dcbz operationDave Liu2006-11-03-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 834x rev1.x silicon has one CPU5 errata. The issue is when the data cache locked with HID0[DLOCK], the dcbz instruction looks like no-op inst. The right behavior of the data cache is when the data cache Locked with HID0[DLOCK], the dcbz instruction allocates new tags in cache. The 834x rev3.0 and later and 8360 have not this bug inside. So, when 834x rev3.0/8360 are working with ECC, the dcbz instruction will corrupt the stack in cache, the processor will checkstop reset. However, the 834x rev1.x can work with ECC with these code, because the sillicon has this cache bug. The dcbz will not corrupt the stack in cache. Really, it is the fault code running on fault sillicon. This patch fix the incorrect dcbz operation. Instead of CPU FP writing to initialise the ECC. CHANGELOG: * Fix the incorrect dcbz operation instead of CPU FP writing to initialise the ECC memory. Otherwise, it will corrupt the stack in cache, The processor will checkstop reset. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Add support for variable flash memory sizes on 83xx systemsTimur Tabi2006-11-03-8/+21
| | | | | | | | | CHANGELOG: * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access window registers, instead of using a hard-coded value of 8MB. Signed-off-by: Timur Tabi <timur@freescale.com>
* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.Marian Balakowicz2006-03-14-0/+34
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* Correct shift offsets in icache_status and dcache_status for MPC83xx.Marian Balakowicz2006-03-14-2/+2
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* Enable address translation on MPC83xxKumar Gala2006-02-10-179/+298
| | | | Patch by Kumar Gala, 10 Feb 2006
* Only disable the MPC83xx watchdog if its enabled out of reset.Kumar Gala2006-01-11-0/+6
| | | | | If its disabled out of reset SW can later enable it if so desired Patch by Kumar Gala, 11 Jan 2006
* Fix style issues primarily in 85xx and 83xx boards.Jon Loeliger2005-08-01-41/+38
| | | | | | | | - C++ comments - Trailing white space - Indentation not by TAB - Excessive amount of empty lines - Trailing empty lines
* * Patch by Eran LibertyEran Liberty2005-07-28-0/+1096
Add support for the Freescale MPC8349ADS board.
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