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* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-918/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* mpc83xx: spd_sdram.c: Disable memory controller before initializingStefan Roese2010-01-07-0/+9
| | | | | | | | | | | | | | | | The memory controller could already be enabled, when spd_sdram() is called. This could be the case for example, when the SDRAM is initialized by the JTAG debugger. The "sync" after the register access via the accessor function is still needed, because the macro uses the sync before the real write is done. So until not all accesses are converted to using accessor functions, this sync still needs to be made "manually" here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd.eu> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Add support for fsl_dma driverPeter Tyser2009-07-02-36/+4
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu> Tested-by: Ira W. Snyder <iws@ovro.caltech.edu> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 83xx: Replace CONFIG_ECC_INIT_VIA_DDRC referencesPeter Tyser2009-07-02-1/+1
| | | | | | | | | | Update 83xx architecture's CONFIG_ECC_INIT_VIA_DDRC references to CONFIG_ECC_INIT_VIA_DDRCONTROLLER, which other Freescale architectures use Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Rename dma_xfer() to dmacpy()Peter Tyser2009-07-01-15/+14
| | | | | | | | Also update dmacpy()'s argument order to match memcpy's and use phys_addr_t/phy_size_t for address/size arguments Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: Add bank configuration to FSL spd_sdram.cJerry Van Baren2009-03-14-6/+10
| | | | | | | | | The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Fix some bugs in spd sdram codeDave Liu2009-03-05-3/+23
| | | | | | | | | | | | | | | | | | | 1. RD_TO_PRE missed to add the AL, and need min 2 clocks for tRTP according to DDR2 JEDEC spec. 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. 3. add the support of DDR2-533,667,800 DIMMs 4. cpo 5. make the AL to min to gain better performance. The Micron MT9HTF6472CHY-667D1 DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. items 1, 2 and 5: Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-14/+14
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc83xx: spd_sdram: fix ddr sdram base address assignment bugAnton Vorontsov2008-09-24-1/+1
| | | | | | | | | | | The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Big white-space cleanup.Wolfgang Denk2008-05-21-1/+1
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc83xx: Update DIMM data bus width test to support 40-bit widthLee Nipper2008-04-11-2/+2
| | | | | | | | 32-bit wide ECC memory modules report 40-bit width. Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: display ddr frequency in board_add_ram_info bannerKim Phillips2008-03-28-4/+7
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: unreinvent mem_clkKim Phillips2008-03-28-5/+5
| | | | | | | delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to mem_*_clk for consistency's sake. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Fix the bug of 266MHz data rate DDRDave Liu2008-01-10-3/+3
| | | | | | | | The DDR doesn't work on the 266MHz data rate, the patch fix the bug. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add the support of MPC837xEMDS boardDave Liu2008-01-08-2/+5
| | | | | | | | | | | The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: fix typo in DDR2 programmingKim Phillips2007-08-17-1/+1
| | | | | | | introduced in the implement board_add_ram_info patch as I was cleaning out the magic numbers. sorry. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: implement board_add_ram_infoKim Phillips2007-08-16-15/+39
| | | | | | | | | | | | | | | | add board_add_ram_info, to make memory diagnostic output more consistent. u-boot banner output now looks like: DRAM: 256 MB (DDR1, 64-bit, ECC on) and for boards with SDRAM on the local bus, a line such as this is added: SDRAM: 64 MB (local bus) also replaced some magic numbers with their equivalent define names. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Suppress the warning 'burstlen'Dave Liu2007-08-10-1/+1
| | | | | | suppress the warning 'burstlen' of spd_sdram. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Correct the burst length for DDR2 with 32 bitsDave Liu2007-08-10-3/+10
| | | | | | The burst length should be 4 for DDR2 with 32 bits bus Signed-off-by: Dave Liu <daveliu@freescale.com>
* Fix memory initialization on MPC8349E-mITXTimur Tabi2007-05-01-5/+0
| | | | | | | | | | | | | Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Michael Benedict <MBenedict@twacs.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Fix two bugs for MPC83xx DDR2 controller SPD InitXie Xiaobo2007-04-12-3/+3
| | | | | | | | There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1.
* mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xxXie Xiaobo2007-03-02-61/+323
| | | | | | | The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
* mpc83xx: U-Boot support for Wind River SBC8349Paul Gortmaker2007-03-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul.
* Code cleanup.Wolfgang Denk2006-11-30-10/+10
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* mpc83xx: Miscellaneous code style fixesTimur Tabi2006-11-28-46/+28
| | | | | | Implement various code style fixes and similar changes. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-2/+2
| | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Fix the incorrect dcbz operationDave Liu2006-11-03-34/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 834x rev1.x silicon has one CPU5 errata. The issue is when the data cache locked with HID0[DLOCK], the dcbz instruction looks like no-op inst. The right behavior of the data cache is when the data cache Locked with HID0[DLOCK], the dcbz instruction allocates new tags in cache. The 834x rev3.0 and later and 8360 have not this bug inside. So, when 834x rev3.0/8360 are working with ECC, the dcbz instruction will corrupt the stack in cache, the processor will checkstop reset. However, the 834x rev1.x can work with ECC with these code, because the sillicon has this cache bug. The dcbz will not corrupt the stack in cache. Really, it is the fault code running on fault sillicon. This patch fix the incorrect dcbz operation. Instead of CPU FP writing to initialise the ECC. CHANGELOG: * Fix the incorrect dcbz operation instead of CPU FP writing to initialise the ECC memory. Otherwise, it will corrupt the stack in cache, The processor will checkstop reset. Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Add MPC8360EMDS basic board supportDave Liu2006-11-03-153/+151
| | | | | Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.
* mpc83xx: Add support for the MPC8349E-mITXTimur Tabi2006-11-03-0/+21
| | | | | | | | | | | | | | | | | | | PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Add support for Errata DDR6 on MPC 834x systemsTimur Tabi2006-11-03-1/+42
| | | | | | | | | | CHANGELOG: * Errata DDR6, which affects all current MPC 834x processors, lists changes required to maintain compatibility with various types of DDR memory. This patch implements those changes. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Changed to unified mpx83xx names and added common 83xx changesDave Liu2006-11-03-125/+188
| | | | | | | Incorporated the common unified variable names and the changes in preparation for releasing mpc8360 patches. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Some code cleanupWolfgang Denk2006-04-16-2/+2
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* Support for DDR with 32-data path. Addotional notes on injectingRafal Jaworowski2006-03-16-12/+49
| | | | multiple-bit errors.
* Add support for ECC DDR initialization on MPC83xx.Marian Balakowicz2006-03-14-22/+108
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* Fix style issues primarily in 85xx and 83xx boards.Jon Loeliger2005-08-01-15/+10
| | | | | | | | - C++ comments - Trailing white space - Indentation not by TAB - Excessive amount of empty lines - Trailing empty lines
* * Patch by Eran LibertyEran Liberty2005-07-28-0/+413
Add support for the Freescale MPC8349ADS board.
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