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* [MIPS] Fix I-/D-cache initialization loopsShinya Kuribayashi2008-03-25-39/+76
| | | | | | | | | | | | | Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I again per a loop for I-cache initialization. But according to 'See MIPS Run', we're encouraged to use three separate loops rather than combining them *for both I- and D-cache*. This patch tries to fix this. In accordance with fixing above, mips_init_[id]cache are separated from mips_cache_reset(), and rewrite cache loops are completely rewritten with useful macros. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* [MIPS] Replace memory clearance code with f_fill64Shinya Kuribayashi2008-03-25-15/+28
| | | | | | This routine fills memory with zero by 64 bytes, and is 64-bit capable. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macrosShinya Kuribayashi2008-03-25-18/+7
| | | | | | | | | | This patch replaces the current function definitions with NESTED, LEAF and END macro. They specify some more additional information about the function; an alignment of symbol, type of symbol, stack frame usage, etc. These information explicitly tells the assembler and the debugger about the types of code we want to generate. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* [MIPS] Request for the 'mips_cache_lock()' removalShinya Kuribayashi2008-03-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial intension of having mips_cache_lock() was to use the cache as memory for temporary stack use so that a C environment can be set up as early as possible. But now mips_cache_lock() follow lowlevel_init(). We've already have the real memory initilaized at this point, therefore we could/should use it. No reason to lock at all. Other problems: Cache locking is not consistent across MIPS implementaions. Some imple- mentations don't support locking at all. The style of locking varies - some support per line locking, others per way, etc. Some parts use bits in status registers instead of cache ops. Current mips_cache_lock() is not necessarily general-purpose. And this is worthy of special mention; once U-Boot/MIPS locks the lines, they are never get unlocked, so the code relies on whatever gets loaded after U-Boot to re-initialize the cache and clear the locks. We're sup- posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented, but leave the situation as it is for a long time. For these reasons, I proposed the removal of mips_cache_lock() from the global start-up code. This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that *things have changed*. If he wants the same behavior as before, he needs to have CFG_INIT_RAM_LOCK_MIPS in his config file. If we don't have any regression report through several releases, then we'll remove codes entirely. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Acked-by: Andrew Dyer <amdyer@gmail.com>
* [MIPS] MIPS 4K core: Coding style cleanupsShinya Kuribayashi2007-11-17-17/+13
| | | | | | No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* * Patch by Steven Scholz, 10 Oct 2003wdenk2003-10-09-3/+3
| | | | | | | | | | - Add support for Altera FPGA ACEX1K * Patches by Thomas Lange, 09 Oct 2003: - Endian swap ATA identity for all big endian CPUs, not just PPC - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize args to linux - add support for dbau1x00 board (MIPS32)
* * Code cleanup:wdenk2003-06-27-2/+1
| | | | | | | | | - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
* Prepare for 0.3.0 releasewdenk2003-04-08-2/+7
| | | | | | * Add support for Purple Board (MIPS64 5Kc) * Add support for MIPS64 5Kc CPUs
* * Patch by Arun Dharankar, 4 Apr 2003:wdenk2003-04-05-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IDMA example code (tested on 8260 only) * Add support for Purple Board (MIPS64 5Kc) * Add support for MIPS64 5Kc CPUs * Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS * Patch by Denis Peter, 04 Apr 2003: - update MIP405-4 board * Patches by Denis Peter, 03 April 2003: - fix PCI IRQs on MPL boards - fix two more un-relocated pointer problems * Fix behaviour of "run" command: - print error message iv variable does not exist - terminate processing of arguments in case of error * Patches by Peter Figuli, 10 Mar 2003 - Add support for BTUART on PXA platform - Add support for WEP EP250 (PXA) board * Fix flash problems on INCA-IP; add tool to allow bruning images to flash using a BDI2000 * Implement fix for I2C Edge Conditions problem for all boards that use the bit-banging driver (common/soft_i2c.c) * Add patches by Robert Schwebel, 31 Mar 2003: - csb226 board: bring in sync with innokom/memsetup.S - csb226 board: fix MDREFR handling - misc doc fixes / extensions - innokom board: cleanup, MDREFR fix in memsetup.S, config update - add BOOT_PROGRESS to armlinux.c
* * Add support for MIPS32 4Kc CPUswdenk2003-03-27-0/+265
* Add support for INCA-IP Board