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path: root/cpu/blackfin/initcode.c
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* Blackfin: support boards with no external memoryMike Frysinger2010-01-17-1/+15
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: re-architect initcodeMike Frysinger2010-01-17-52/+169
| | | | | | | | The single initcode function was growing unwieldy, so split it up the distinct steps into their own function. This should making digesting the result much easier on people. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: fix booting with older bootroms (no EVT1)Mike Frysinger2009-05-06-0/+2
| | | | | | | | | | | When dropping jump block support, the assumption was that all bootroms supported entry point redirection via the EVT1 register. Unfortunately, this turned out to be incorrect for the oldest Blackfin parts (BF533-0.2 and older and BF561). No one really noticed earlier because these parts usually are booted by bypassing the bootrom entirely, and older BF533 parts are not supported at all (too many anomalies). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: recurse with early serial initcodeMike Frysinger2009-05-06-1/+1
| | | | | | | Make sure we recurse through serial_putc() rather than bang on the UART transmit register directly to avoid hardware overflows when using \n. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add check for anomaly 05000362Mike Frysinger2009-04-06-0/+9
| | | | | | | | | | | | | | | DESCRIPTION: The column address width settings for banks 2 and 3 are misconnected in the SDRAM controller. Accesses to bank 2 will result in an error if the Column Address Width for bank 3 (EB3CAW ) is not set to be the same as that of bank 2. WORKAROUND: If using bank 2, make sure that banks 2 and 3 have the same column address width settings in the EBIU_SDBCTL register. This must be the case regardless of whether or not bank 3 is enabled. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add comment about anomaly 05000430 avoidanceMike Frysinger2009-04-06-0/+2
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add workaround for anomaly 05000242Mike Frysinger2009-04-06-1/+1
| | | | | | | | | | | | | DESCRIPTION: If the DF bit is set prior to a hardware reset, the PLL will continue to divide CLKIN by 2 after the hardware reset, but the DF bit itself will be cleared in the PLL_CTL register. WORKAROUND: Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by 2 after reset. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add workaround for anomaly 05000171Mike Frysinger2009-04-06-0/+4
| | | | | | | | | | | | | DESCRIPTION: The Boot ROM is executed at power up/reset and changes the value of the SICA_IWR registers from their default reset value of 0xFFFF, but does not restore them. WORKAROUND: User code should not rely on the default value of these registers. Set the desired values explicitly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: fix crash when booting from external memoryMike Frysinger2009-04-02-0/+9
| | | | | | | | | When testing a u-boot binary that hasn't been booted from the bootrom, we have to make sure the bootstruct structure has sane storage space. If we don't, the initcode will crash when it tries to dereference an invalid pointer. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: put memory into self-refresh before/after programming clocksMike Frysinger2009-03-23-49/+140
| | | | | | | | | | | When initializing the core clocks, stick external memory into self-refresh. This gains us a few cool things: - support suspend-to-RAM with Linux - reprogram clocks automatically when doing "go" on u-boot.bin in RAM - make sure settings are stable before flashing new version - finally fully unify initialize startup code path between LDR/non-LDR Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: do not program voltage regulator on parts that do not have oneMike Frysinger2009-03-23-3/+20
| | | | | | | Some newer Blackfins (like the BF51x) do not have an on-chip voltage regulator, so do not attempt to program the memory as if it does. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllersMike Frysinger2009-03-23-0/+33
| | | | | | | If the board config does not specify an explicit EBIU_SDBCTL value, set it up with sane values based on other configuration options. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: handle reboot anomaly 432Mike Frysinger2009-03-23-0/+6
| | | | | | | | | | | Workaround anomaly 432: The bfrom_SysControl() firmware function does not clear the SIC_IWR1 register before executing the PLL programming sequence. Therefore, any interrupt enabled in the SIC_IWR1 register prior to the call to bfrom_SysControl() can prematurely terminate the idle sequence required for the PLL to relock properly. SIC_IWR0 is properly handled. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: kill off LDR jump blockMike Frysinger2009-03-23-0/+4
| | | | | | | The Boot ROM uses EVT1 as the entry point so set that rather than having to use a tiny jump block in the default EVT1 location. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: disable syscontrol code for nowMike Frysinger2009-02-21-0/+1
| | | | | | | | | | Looks like the initcode updates fell out of order during my merges. The patch that really fixes up this code is part of power-on overhaul and so is too large for merging at this point. Instead, we can disable the code as no currently in-tree board depends on it. The next merge window will fix things up properly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: dynamically update UART speed when initializingMike Frysinger2009-02-05-38/+24
| | | | | | | | | Previously, booting over the UART required the baud rate to be known ahead of time. Using a bit of tricky simple math, we can calculate the new board rate based on the old divisors. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
* Blackfin: add support for fast SPI reads with Boot ROMMike Frysinger2009-02-05-8/+17
| | | | | | | Newer Blackfin boot roms support using the fast SPI read command rather than just the slow one. If the functionality is available, then use it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: check for reserved settings in DDR MMRsMike Frysinger2009-02-05-0/+7
| | | | | | | Some bits of the DDR MMRs should not be set. If they do, bad things may happen (like random failures or hardware destruction). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: set default voltage levels for BF538/BF539 partsMike Frysinger2009-02-05-0/+3
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: use on-chip syscontrol() rom function when availableMike Frysinger2009-02-05-22/+38
| | | | | | | | Newer Blackfin's have an on-chip rom with a syscontrol() function that needs to be used to properly program the memory and voltage settings as it will include (possibly critical) factory tested bias values. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: dont check baud if it wont actually get usedMike Frysinger2009-02-02-1/+5
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: respect CONFIG_CLKIN_HALFMike Frysinger2009-01-28-1/+1
| | | | | | | | As pointed out by Ivan Koryakovskiy, the initialization code was not actually respecting the CONFIG_CLKIN_HALF option when configuring the PLL_CTL register. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: unify cpu and boot modesMike Frysinger2008-03-30-0/+353
All of the duplicated code for Blackfin processors and boot modes have been unified. After all, the core is the same for all processors, just the peripheral set differs (which gets handled in the drivers). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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