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* Add AVR32 LCD supportMark Jackson2009-07-26-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the AVR32 LCD controller. This patch is based off the latest u-boot-video. A quick summary of what's going on:- Enable LCDC pixel clock Enable LCDC port pins Add framebuffer pointer to global_data struct Allocate framebuffer To use the new code, update your board config to include something like this:- #define CONFIG_LCD 1 #if defined(CONFIG_LCD) #define CONFIG_CMD_BMP #define CONFIG_ATMEL_LCD 1 #define LCD_BPP LCD_COLOR16 #define CONFIG_BMP_16BPP 1 #define CONFIG_FB_ADDR 0x10600000 #define CONFIG_WHITE_ON_BLACK 1 #define CONFIG_VIDEO_BMP_GZIP 1 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144 #define CONFIG_ATMEL_LCD_BGR555 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 #define CONFIG_SPLASH_SCREEN 1 #endif The standard U-Boot BMP and Splash-screen features should just work. Signed-off-by: Mark Jackson <mpfj@mimc.co.uk> [agust@denx.de: fixed some style issues] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* AVR32: Make cacheflush cpu-dependentOlav Morken2009-02-23-1/+1
| | | | | | | | | | | The AT32UC3A series of processors doesn't contain any cache, and issuing cache control instructions on those will cause an exception. This commit makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support. Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com> Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com> Signed-off-by: Olav Morken <olavmrk@gmail.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* Merge branch 'fixes' into cleanupsHaavard Skinnemoen2008-12-17-26/+26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/atmel/atngw100/atngw100.c board/atmel/atstk1000/atstk1000.c cpu/at32ap/at32ap700x/gpio.c include/asm-avr32/arch-at32ap700x/clk.h include/configs/atngw100.h include/configs/atstk1002.h include/configs/atstk1003.h include/configs/atstk1004.h include/configs/atstk1006.h include/configs/favr-32-ezkit.h include/configs/hammerhead.h include/configs/mimc200.h
| * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-28/+28
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | avr32: Add support for "GPIO" port muxHaavard Skinnemoen2008-09-01-0/+108
| | | | | | | | | | | | | | | | The "GPIO" port mux is used on AVR32 UC3 parts as well as AT32AP7200 and all later AVR32 chips. This patch adds a driver for it, implementing the same API as the existing portmux-pio driver but with more functionality. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | avr32: Use board_postclk_init instead of gclk_initHaavard Skinnemoen2008-09-01-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the avr32-specific gclk_init() board hook with the standard board_postclk_init() hook which is supposed to run at the same point during initialization. Provide a dummy weak alias for boards not implementing this hook. The cost of this is: - 2 bytes for the dummy function (retal 0) - 2 bytes for each unnecessary function call (short rcall) which is a pretty small price to pay for avoiding lots of #ifdef clutter. In this particular case, all boards probably end up slightly smaller because we avoid the conditional checking if the gclk_init symbol is NULL. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | avr32: Add gclk helper functionsHaavard Skinnemoen2008-09-01-0/+25
| | | | | | | | | | | | | | | | | | | | | | Add two helper functions for configuring and enabling generic clocks: - gclk_enable_output: Enables output on a GCLKx pin - gclk_set_rate: Configures a gclk to run at a specific rate This should eliminate any reason to go mucking about with PM registers from board code. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | avr32: refactor the portmux/gpio codeHaavard Skinnemoen2008-09-01-317/+298
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Separate the portmux configuration functionality from the GPIO pin control API. - Separate the controller-specific code from the chip-specific code. - Allow "ganged" port configuration (multiple pins at once). - Add more flexibility to the "canned" peripheral select functions: - Allow using more than 23 address bits, more chip selects, as well as NAND- and CF-specific pins. - Make the MACB SPEED pin optional, and choose between MII/RMII using a parameter instead of an #ifdef. - Make it possible to use other MMC slots than slot 0, and support different MMC/SDCard data bus widths. - Use more reasonable pull-up defaults; floating pins may consume a lot of power. - Get rid of some custom portmux code from the mimc200 board code. The old gpio/portmux API couldn't really handle its requirements, but the new one can. - Add documentation. The end result is slightly smaller code for all boards. Which isn't really the point, but at least it isn't any larger. This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if the board maintainers could help me test this on their boards. In particular, the mimc200 port has lost a lot of code, so I'm hoping Mark can help me out. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Cc: Mark Jackson <mpfj@mimc.co.uk> Cc: Alex Raimondi <alex.raimondi@miromico.ch> Cc: Julien May <julien.may@miromico.ch> Changes since v1: * Enable pullup on NWAIT * Add missing include to portmux-pio.h * Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs
* Add support for the hammerhead (AVR32) boardJulien May2008-07-30-1/+4
| | | | | | | | | | | | | | | | | | | | | The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* mmc: Move atmel_mci driver into drivers/mmcHaavard Skinnemoen2008-07-10-750/+0
| | | | | | | This makes it easier to use the driver on other platforms. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Acked-by: Jean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driverHaavard Skinnemoen2008-07-10-1/+1
| | | | | | | | | After we move the atmel_mci driver into drivers/mmc, we can't select it with CONFIG_MMC anymore. Introduce a new symbol specifically for this driver so that there's no ambiguity. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Acked-by: Jean-Chritophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-avr32Wolfgang Denk2008-07-07-22/+90
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| * avr32: Fix SPI portmux initializationHaavard Skinnemoen2008-06-20-22/+34
| | | | | | | | | | | | | | Use the new GPIO manipulation functions to set up the chip select lines, and make sure both busses use GPIO for chip select control. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * avr32: Add GPIO manipulation functionsPeter Ma2008-06-20-0/+56
| | | | | | | | | | | | | | | | Adds GPIO manipulation functions for AVR32 AP7 platform. Signed-off-by: Peter Ma <pma@mediamatech.com> [haavard.skinnemoen@atmel.com: coding style fixup, slight simplification] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | MMC: Consolidate MMC/SD command definitionsHaavard Skinnemoen2008-06-28-2/+2
|/ | | | | | | | | | | | | | | This moves the MMC and SD Card command definitions from include/asm/arch/mmc.h into include/mmc.h. These definitions are given by the MMC and SD Card standards, not by any particular architecture. There's a lot more room for consolidation in the MMC drivers which I'm hoping to get done eventually, but this patch is a start. Compile-tested for all avr32 boards as well as lpc2292sodimm and lubbock. This should cover all three mmc drivers in the tree. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* atmel_spi: Driver for the Atmel SPI controllerHans-Christian Egtvedt2008-06-03-0/+43
| | | | | | | | | | | | | | | This adds a driver for the SPI controller found on most AT91 and AVR32 chips, implementing the new SPI API. Changed in v4: - Update to new API - Handle zero-length transfers appropriately. The user may send a zero-length SPI transfer with SPI_XFER_END set in order to deactivate the chip select after a series of transfers with chip select active. This is useful e.g. when polling the status register of DataFlash. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* avr32: Fix theoretical race in udelay()Haavard Skinnemoen2008-05-27-9/+7
| | | | | | | | | | | If the specified delay is very short, the cycle counter may go past the "end" time we are waiting for before we get around to reading it. Fix it by checking the different between the cycle count "now" and the cycle count at the beginning. This will work as long as the delay measured in number of cycles is below 2^31. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Compile atmel_mci.o conditionallyHaavard Skinnemoen2008-05-27-5/+1
| | | | | | | Remove #ifdef CONFIG_MMC from the source file and use conditional compilation in the Makefile instead. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Fix wrong error flags in atmel_mci driverHaavard Skinnemoen2008-05-27-1/+1
| | | | | | | | Make sure we check for CRC errors when sending commands that use CRC checking. Reported-by: Gururaja Hebbar K R <gururajakr@sanyo.co.in> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Fix two warnings in atmel_mci.cHaavard Skinnemoen2008-05-27-2/+4
| | | | | | The warnings are harmless but annoying. Let's fix them. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Rework SDRAM initialization codeHaavard Skinnemoen2008-05-27-63/+39
| | | | | | | | | | | | | | This cleans up the SDRAM initialization and related code a bit, and allows faster booting. * Add definitions for EBI and internal SRAM to asm/arch/memory-map.h * Remove memory test from sdram_init() and make caller responsible for verifying the SDRAM and determining its size. * Remove base_address member from struct sdram_config (was sdram_info) * Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT * Add support for a common STK1000 hack: 16MB SDRAM instead of 8. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Do stricter stack checking in the exception handlerHaavard Skinnemoen2008-05-27-1/+2
| | | | | | | Don't do a stack dump if the stack pointer is outside the memory area reserved for stack. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Use the same entry point for reset and exception handlingHaavard Skinnemoen2008-05-27-74/+120
| | | | | | | | | | | | | | Since the reset vector is always aligned to a very large boundary, we can save a couple of KB worth of alignment padding by placing the exception vectors at the same address. Deciding which one it is is easy: If we're handling an exception, the CPU is in Exception mode. If we're starting up after reset, the CPU is in Supervisor mode. So this adds a very minimal overhead to the reset path (only executed once) and the exception handling path (normally never executed at all.) Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Rename pm_init() as clk_init() and make SoC-specificHaavard Skinnemoen2008-05-27-44/+74
| | | | | | | | pm_init() was always more about clock initialization than anything else. Dealing with PLLs, clock gating and such is also inherently SoC-specific, so move it into a SoC-specific directory. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Use new-style Makefile for the at32ap platformHaavard Skinnemoen2008-05-27-7/+14
| | | | | | This makes it easier to avoid compiling certain files later. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Remove unused file cpu/at32ap/pm.cHaavard Skinnemoen2008-05-27-42/+0
| | | | Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Get rid of the .flashprog sectionHaavard Skinnemoen2008-05-27-6/+0
| | | | | | | | | | | | The .flashprog section was only needed back when we were running directly from flash, and it's even more useless on NGW100 since it uses the CFI flash driver which never used this workaround in the first place. Remove it on STK1000 as well, and get rid of all the associated code and annotations. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Disable the AP7000 internal watchdog on startupDavid Brownell2008-05-27-0/+4
| | | | | | | | | This patch forces the watchdog off in all cases. That will at least get rid of the constant reboot cycle, though it won't let the watchdog actually run in the new kernels: its probe() comes up with a polite warning. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* AVR32: Make SDRAM refresh rate configurableHaavard Skinnemoen2008-02-05-1/+5
| | | | | | | | | | | | | | The existing code assumes the SDRAM row refresh period should always be 15.6 us. This is not always true, and indeed on the ATNGW100, the refresh rate should really be 7.81 us. Add a refresh_period member to struct sdram_info and initialize it properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will panic() until the refresh_period member is updated properly. Big thanks to Gerhard Berghofer for pointing out this issue. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* AVR32: Fix wrong pin setup for USART3Haavard Skinnemoen2007-12-17-1/+1
| | | | | | | | | | | | As reported by Gerhard Berghofer: in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 instead of PB18 and PB19. which is obviously correct. There's currently no code that uses USART3, but custom boards may run into problems. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* AVR32: Make some AT32AP700x peripherals optionalHaavard Skinnemoen2007-12-17-0/+7
| | | | | | | | | | | Add a chip-features file providing definitions of the form AT32AP700x_CHIP_HAS_<peripheral> to indicate the availability of the given peripheral on the currently selected chip. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* AVR32: Rename at32ap7000 -> at32ap700xHaavard Skinnemoen2007-12-17-0/+0
| | | | | | | | | The SoC-specific code for all the AT32AP700x CPUs is practically identical; the only difference is that some chips have less features than others. By doing this rename, we can add support for the AP7000 derivatives simply by making some features conditional. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* atmel_mci: Show SR when block read failsHaavard Skinnemoen2007-12-17-6/+7
| | | | | | | Show controller status as well as card status when an error occurs during block read. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* atmel_mci: Fix data timeout valueHaavard Skinnemoen2007-08-13-0/+59
| | | | | | | | | Calculate the data timeout based on values from the CSD instead of just using a hardcoded DTOR value. This is a backport of a similar fix in BSP 2.0, with one additional fix: the DTOCYC value is rounded up instead of down. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* AVR32: Include <div64.h> instead of <asm/div64.h>Haavard Skinnemoen2007-08-13-1/+1
| | | | | | | | | | | include/asm-avr32/div64.h was recently moved to include/div64.h, but cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of the patch was merged perhaps?) This patch updates cpu/at32ap/interrupts.c so that the avr32 port compiles again. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* atmel_mci: Use 512 byte blocksize if possibleHaavard Skinnemoen2007-08-13-4/+21
| | | | | | | | | | | | Instead of always using the largest blocksize the card supports, check if it can support smaller block sizes and use 512 bytes if possible. Most cards do support this, and other parts of u-boot seem to have trouble with block sizes different from 512 bytes. Also enable underrun/overrun protection. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Acked-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
* Merge with /home/wd/git/u-boot/custodian/u-boot-avr32; code cleanup.Wolfgang Denk2007-04-18-898/+1022
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| * Atmel MCI driverHaavard Skinnemoen2007-04-14-1/+675
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver for the Atmel MCI controller (MMC interface) for AT32AP CPUs. The AT91 ARM-based CPUs use basically the same hardware, so it should be possible to share this driver, but no effort has been made so far. Hardware documentation can be found in the AT32AP7000 data sheet, which can be downloaded from http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * AVR32: Add clk and gpio infrastructure for mmciHaavard Skinnemoen2007-04-14-0/+10
| | | | | | | | | | | | | | Implement functions for configuring the mmci pins, as well as functions for getting the clock rate of the mmci controller. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * AVR32: Add clk and gpio infrastructure for macb0 and macb1Haavard Skinnemoen2007-04-14-0/+50
| | | | | | | | | | | | | | | | Implement functions for configuring the macb0 and macb1 pins, as well as functions for getting the clock rate of the various busses the macb ethernet controllers are connected to. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * AVR32: Relocate u-boot to SDRAMHaavard Skinnemoen2007-04-14-36/+90
| | | | | | | | | | | | | | Relocate the u-boot image into SDRAM like everyone else does. This means that we can handle much larger .data and .bss than we used to. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * AVR32: Resource management rewriteHaavard Skinnemoen2007-04-14-862/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite the resource management code (i.e. I/O memory, clock gating, gpio) so it doesn't depend on any global state. This is necessary because this code is heavily used before relocation to RAM, so we can't write to any global variables. As an added bonus, this makes u-boot's memory footprint a bit smaller, although some functionality has been left out; all clocks are enabled all the time, and there's no checking for gpio line conflicts. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
| * AVR32: Split start_u_boot into board_init_f and board_init_rHaavard Skinnemoen2007-04-14-1/+1
|/ | | | | | | | | Split the avr32 initialization code into a function to run before relocation, board_init_f and a function to run after relocation, board_init_r. For now, board_init_f simply calls board_init_r at the end. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* Fix "ar" flags in some Makefiles to allow for silent "make -s"Wolfgang Denk2006-10-27-2/+2
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* Add AT32AP CPU and AT32AP7000 SoC supportWolfgang Denk2006-10-24-0/+2287
Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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