arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	AVR32: Make cacheflush cpu-dependent	Olav Morken	2009-02-23	-1/+1
\| \| \| \| \| \| \| \| \| \| \|	The AT32UC3A series of processors doesn't contain any cache, and issuing cache control instructions on those will cause an exception. This commit makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support. Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com> Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com> Signed-off-by: Olav Morken <olavmrk@gmail.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
*	rename CFG_ macros to CONFIG_SYS	Jean-Christophe PLAGNIOL-VILLARD	2008-10-18	-4/+4
\| \| \| \|	Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*	Add AT32AP CPU and AT32AP7000 SoC support	Wolfgang Denk	2006-10-24	-0/+97
	Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>