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* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-14/+14
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Add support for the hammerhead (AVR32) boardJulien May2008-07-30-1/+1
| | | | | | | | | | | | | | | | | | | | | The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Fix SPI portmux initializationHaavard Skinnemoen2008-06-20-22/+34
| | | | | | | Use the new GPIO manipulation functions to set up the chip select lines, and make sure both busses use GPIO for chip select control. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* atmel_spi: Driver for the Atmel SPI controllerHans-Christian Egtvedt2008-06-03-0/+43
| | | | | | | | | | | | | | | This adds a driver for the SPI controller found on most AT91 and AVR32 chips, implementing the new SPI API. Changed in v4: - Update to new API - Handle zero-length transfers appropriately. The user may send a zero-length SPI transfer with SPI_XFER_END set in order to deactivate the chip select after a series of transfers with chip select active. This is useful e.g. when polling the status register of DataFlash. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* avr32: Rename pm_init() as clk_init() and make SoC-specificHaavard Skinnemoen2008-05-27-1/+273
| | | | | | | | pm_init() was always more about clock initialization than anything else. Dealing with PLLs, clock gating and such is also inherently SoC-specific, so move it into a SoC-specific directory. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* AVR32: Fix wrong pin setup for USART3Haavard Skinnemoen2007-12-17-1/+1
| | | | | | | | | | | | As reported by Gerhard Berghofer: in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 instead of PB18 and PB19. which is obviously correct. There's currently no code that uses USART3, but custom boards may run into problems. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* AVR32: Make some AT32AP700x peripherals optionalHaavard Skinnemoen2007-12-17-0/+7
| | | | | | | | | | | Add a chip-features file providing definitions of the form AT32AP700x_CHIP_HAS_<peripheral> to indicate the availability of the given peripheral on the currently selected chip. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* AVR32: Rename at32ap7000 -> at32ap700xHaavard Skinnemoen2007-12-17-0/+180
The SoC-specific code for all the AT32AP700x CPUs is practically identical; the only difference is that some chips have less features than others. By doing this rename, we can add support for the AP7000 derivatives simply by making some features conditional. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>