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* Convert CONFIG_SPL_NET_SUPPORT to KconfigSimon Glass2016-09-16-0/+5
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_NET_VCI_STRING to KconfigSimon Glass2016-09-16-0/+4
| | | | | | | This converts the following to Kconfig: CONFIG_SPL_NET_VCI_STRING Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_NAND_SUPPORT to KconfigSimon Glass2016-09-16-1/+109
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_MUSB_NEW_SUPPORT to KconfigSimon Glass2016-09-16-0/+8
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_MTD_SUPPORT to KconfigSimon Glass2016-09-16-9/+30
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT to KconfigSimon Glass2016-09-16-0/+101
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_MMC_SUPPORT to KconfigSimon Glass2016-09-16-0/+98
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBGENERIC_SUPPORT to KconfigSimon Glass2016-09-16-0/+215
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBDISK_SUPPORT to KconfigSimon Glass2016-09-16-0/+51
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBCOMMON_SUPPORT to KconfigSimon Glass2016-09-16-0/+214
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_I2C_SUPPORT to KconfigSimon Glass2016-09-16-3/+229
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_GPIO_SUPPORT to KconfigSimon Glass2016-09-16-0/+92
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_FAT_SUPPORT to KconfigSimon Glass2016-09-16-0/+34
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_EXT_SUPPORT to KconfigSimon Glass2016-09-16-1/+49
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_ETH_SUPPORT to KconfigSimon Glass2016-09-16-2/+6
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_ENV_SUPPORT to KconfigSimon Glass2016-09-16-5/+114
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to KconfigSimon Glass2016-09-16-0/+63
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_DMA_SUPPORT to KconfigSimon Glass2016-09-16-1/+10
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_HASH_SUPPORT to KconfigSimon Glass2016-09-16-0/+2
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_CRYPTO_SUPPORT to KconfigSimon Glass2016-09-16-0/+2
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* spear: Use upper case for CONFIG optionsSimon Glass2016-09-16-21/+21
| | | | | | | | | There are a few options which use lower case. We should use upper case for all CONFIG options. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add usbtty/nand hunk to include/configs/spear3xx_evb.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* Move existing use of CONFIG_SPL_RSA to KconfigSimon Glass2016-09-16-0/+51
| | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
* Move existing use of CONFIG_SPL_DM to KconfigSimon Glass2016-09-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org>
* Kconfig: Move SPL settings into their own fileSimon Glass2016-09-16-396/+396
| | | | | | Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
* Correct defconfigs using savedefconfigSimon Glass2016-09-16-1/+3
| | | | | | | | | Update the defconfig files to match their canonical form, as produced by 'make safedefconfig'. This is the result of running 'tools/moveconfig.py -s' on the tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* common, kconfig: move VERSION_VARIABLE to KconfigHeiko Schocher2016-09-09-4/+212
| | | | | | | move VERSION_VARIABLE from board config file into a Kconfig option. Signed-off-by: Heiko Schocher <hs@denx.de>
* configs: Migrate CONFIG_USB_STORAGETom Rini2016-09-09-0/+1052
| | | | | | | In some cases we were missing CONFIG_USB=y so enable that when needed. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2016-09-09-549/+392
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-09-09-1/+104
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| * warp7: Add a secure mode targetFabio Estevam2016-09-06-0/+36
| | | | | | | | | | | | | | NXP kernel expects to boot in secure mode, so introduce warp7_secure_defconfig target which selects CONFIG_ARMV7_BOOT_SEC_DEFAULT. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * warp: Fix RAM size runtime detectionFabio Estevam2016-09-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a13d3757f7df ("warp: Use imx_ddr_size() for calculating the DDR size") warp board no longer boots. The reason for the breakage is that the warp board is using the DDR configuration from mx6slevk. A fundamental difference between warp and mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two. The imx_ddr() function calculates the RAM size in runtime by reading the values of registers MDCTL and MDMISC. So in order to fix this warp boot issue, create a imximage DDR file specific to warp, where the MDCTL register is configured to only activates a single chip select. Reported-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Breno Lima <breno.lima@nxp.com>
| * arm: imx: Add support for Advantech DMS-BA16 boardAkshay Bhat2016-09-06-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
* | Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROLMasahiro Yamada2016-09-07-24/+0
| | | | | | | | | | | | | | | | | | | | | | If both SPL_DM and SPL_OF_CONTROL are enabled, SPL needs to bind several devices, but CONFIG_SYS_MALLOC_F_LEN=0x400 is apparently not enough. Increase the default to 0x2000 for the case. This will be helpful for shorter defconfigs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | configs: am4xhs: Modify SPL load address to fix UART boot issueMadan Srinivas2016-09-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An issue in the TI secure image generation tool causes the ROM to load the SPL at a different load address than what is specified by CONFIG_ISW_ENTRY_ADDR while doing a peripheral boot on HS devices. This causes the SPL to fail on secure devices during peripheral boot. The TI secure image generation tool has been fixed so that the SPL will always be loaded at 0x403018E0 by the ROM code for both peripheral and memory boot modes. Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: AM57xx: Enable post-processing of FIT artifacts loaded by U-BootAndreas Dannenberg2016-09-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI AM57xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7xx: Enable post-processing of FIT artifacts loaded by U-BootAndreas Dannenberg2016-09-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI DRA7xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: AM43xx: Enable post-processing of FIT artifacts loaded by U-BootAndreas Dannenberg2016-09-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI AM43xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | meson: odroid-c2: enable Ethernet support through the device treeBeniamino Galvani2016-09-06-0/+3
| | | | | | | | | | | | | | | | Remove the device definition from board file, update the driver with the new compatible property and update config with necessary options. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | serial: bcm283x_mu: Detect disabled serial deviceAlexander Graf2016-09-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the raspberry pi, you can disable the serial port to gain dynamic frequency scaling which can get handy at times. However, in such a configuration the serial controller gets its rx queue filled up with zero bytes which then happily get transmitted on to whoever calls getc() today. This patch adds detection logic for that case by checking whether the RX pin is mapped to GPIO15 and disables the mini uart if it is not mapped properly. That way we can leave the driver enabled in the tree and can determine during runtime whether serial is usable or not, having a single binary that allows for uart and non-uart operation. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sunxi: Add defconfig and dts file for the Orange Pi Plus2E SBCHans de Goede2016-09-03-0/+19
| | | | | | | | | | | | | | | | | | | | | | The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus, with 2G RAM and an external gbit ethernet phy. The dts file is identical to the one submitted to the upstream kernel, except that it has the pending patch to enable the ethernet controller squashed in, as u-boot already has sun8i-emac support. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Enable emac on H3 orangepi boardsHans de Goede2016-09-03-1/+3
| | | | | | | | | | | | | | The Orange Pi 2 and Orange Pi Plus also come with ethernet, enable support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add support for A33-OLinuXino boardStefan Mavrodiev2016-09-03-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A33-OLinuXino is A33 development board designed by Olimex LTD. It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector, headphone and mic jacks, connector for LiPo battery and optional 4GB NAND Flash. It has two 40-pin headers. One for LCD panel, and one for additional modules. Also there is CSI/DSI connector. The dts files are identical to the ones submitted to the upstream kernel. Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add iNet D978 rev2 defconfigIcenowy Zheng2016-09-03-0/+26
|/ | | | | | | | | | The iNet D978 rev2 is a tablet board designed by iNet, which is intended to use on 10" tablets with a appearance like Apple iPad. It has A33 SoC, 1GB RAM, 8GB/16GB NAND, SDIO Wi-Fi, a MicroUSB port and a MicroSD slot. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: tegra: Add support for TK1-SOM board from Colorado EngineeringPeter Chubb2016-09-01-0/+47
| | | | | | | | | | | | | | The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: use numeric versioning for p2771-0000Stephen Warren2016-08-30-4/+4
| | | | | | | | | | | | | | | | | The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric versioning scheme, with version numbers such as 000/100/200/300/400/500. Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00. However, that numbering scheme is not easily visible outside of NVIDIA, and so does not make much sense to use. Convert U-Boot to use the readily visible numeric scheme. Also, it turns out that the current A02 DT actually applies to board versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200 so that all U-Boot builds are named after the first version of the HW they support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* x86: qemu: efi: Add two boards for EFI 32-bit and 64-bit payloadBin Meng2016-08-30-0/+97
| | | | | | | | | | | This introduces two board defconfig files for generating EFI 32-bit and 64-bit payloads, to run on QEMU x86 target. With these in place, hopefully buildman will catch any build error with EFI payload support on x86. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-08-28-6/+7
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| * ARM: uniphier: enable CONFIG_CMD_CACHEMasahiro Yamada2016-08-28-0/+6
| | | | | | | | | | | | | | This will be useful, for example, to load firmware to DRAM and make it visible to other agents. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: change UNIPHIER_SERIAL to default y optionMasahiro Yamada2016-08-28-6/+0
| | | | | | | | | | | | | | This is very likely to be necessary for normal use cases. Set its default to 'y' for shorter defconfig files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN for sLD3Masahiro Yamada2016-08-28-0/+1
| | | | | | | | | | | | | | | | | | | | Commit 76c52ce29fd7 ("ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes") missed to increase this config for sLD3. This change is needed to add "u-boot,dm-pre-reloc" to some nodes; more devices are bound, more malloc memory is needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-05 06:16:02 +0000