summaryrefslogtreecommitdiff
path: root/configs
Commit message (Collapse)AuthorAgeLines
...
| * | sunxi: Add mmc0 card detect pin for Sinlinx SinA33Chen-Yu Tsai2016-09-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 uses PB4 for mmc0 card detect. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add defconfig and dts for the NanoPi NEOJelle van der Waa2016-09-18-0/+16
| |/ | | | | | | | | | | | | | | | | The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb and one usb OTG connector. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Convert CONFIG_SPL_YMODEM_SUPPORT to KconfigSimon Glass2016-09-16-0/+31
| | | | | | | | | | | | | | | | Convert CONFIG_SPL_YMODEM_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_WATCHDOG_SUPPORT to KconfigSimon Glass2016-09-16-0/+56
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_USB_SUPPORT to KconfigSimon Glass2016-09-16-0/+1
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_USB_HOST_SUPPORT to KconfigSimon Glass2016-09-16-1/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_USBETH_SUPPORT to KconfigSimon Glass2016-09-16-1/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SPI_SUPPORT to KconfigSimon Glass2016-09-16-0/+69
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SPI_FLASH_SUPPORT to KconfigSimon Glass2016-09-16-0/+72
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass2016-09-16-58/+295
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SATA_SUPPORT to KconfigSimon Glass2016-09-16-0/+1
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_POWER_SUPPORT to KconfigSimon Glass2016-09-16-21/+32
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_ONENAND_SUPPORT to KconfigSimon Glass2016-09-16-0/+4
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_NOR_SUPPORT to KconfigSimon Glass2016-09-16-0/+11
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_NET_SUPPORT to KconfigSimon Glass2016-09-16-0/+5
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_NET_VCI_STRING to KconfigSimon Glass2016-09-16-0/+4
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_NET_VCI_STRING Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_NAND_SUPPORT to KconfigSimon Glass2016-09-16-1/+109
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_MUSB_NEW_SUPPORT to KconfigSimon Glass2016-09-16-0/+8
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_MTD_SUPPORT to KconfigSimon Glass2016-09-16-9/+30
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT to KconfigSimon Glass2016-09-16-0/+101
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_MMC_SUPPORT to KconfigSimon Glass2016-09-16-0/+98
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_LIBGENERIC_SUPPORT to KconfigSimon Glass2016-09-16-0/+215
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_LIBDISK_SUPPORT to KconfigSimon Glass2016-09-16-0/+51
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_LIBCOMMON_SUPPORT to KconfigSimon Glass2016-09-16-0/+214
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_I2C_SUPPORT to KconfigSimon Glass2016-09-16-3/+229
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_GPIO_SUPPORT to KconfigSimon Glass2016-09-16-0/+92
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_FAT_SUPPORT to KconfigSimon Glass2016-09-16-0/+34
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_EXT_SUPPORT to KconfigSimon Glass2016-09-16-1/+49
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_ETH_SUPPORT to KconfigSimon Glass2016-09-16-2/+6
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_ENV_SUPPORT to KconfigSimon Glass2016-09-16-5/+114
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to KconfigSimon Glass2016-09-16-0/+63
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_DMA_SUPPORT to KconfigSimon Glass2016-09-16-1/+10
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_HASH_SUPPORT to KconfigSimon Glass2016-09-16-0/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_CRYPTO_SUPPORT to KconfigSimon Glass2016-09-16-0/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | spear: Use upper case for CONFIG optionsSimon Glass2016-09-16-21/+21
| | | | | | | | | | | | | | | | | | There are a few options which use lower case. We should use upper case for all CONFIG options. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add usbtty/nand hunk to include/configs/spear3xx_evb.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Move existing use of CONFIG_SPL_RSA to KconfigSimon Glass2016-09-16-0/+51
| | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Move existing use of CONFIG_SPL_DM to KconfigSimon Glass2016-09-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Kconfig: Move SPL settings into their own fileSimon Glass2016-09-16-396/+396
| | | | | | | | | | | | Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Correct defconfigs using savedefconfigSimon Glass2016-09-16-1/+3
|/ | | | | | | | | Update the defconfig files to match their canonical form, as produced by 'make safedefconfig'. This is the result of running 'tools/moveconfig.py -s' on the tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* common, kconfig: move VERSION_VARIABLE to KconfigHeiko Schocher2016-09-09-4/+212
| | | | | | | move VERSION_VARIABLE from board config file into a Kconfig option. Signed-off-by: Heiko Schocher <hs@denx.de>
* configs: Migrate CONFIG_USB_STORAGETom Rini2016-09-09-0/+1052
| | | | | | | In some cases we were missing CONFIG_USB=y so enable that when needed. Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2016-09-09-549/+392
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-09-09-1/+104
|\
| * warp7: Add a secure mode targetFabio Estevam2016-09-06-0/+36
| | | | | | | | | | | | | | NXP kernel expects to boot in secure mode, so introduce warp7_secure_defconfig target which selects CONFIG_ARMV7_BOOT_SEC_DEFAULT. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * warp: Fix RAM size runtime detectionFabio Estevam2016-09-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a13d3757f7df ("warp: Use imx_ddr_size() for calculating the DDR size") warp board no longer boots. The reason for the breakage is that the warp board is using the DDR configuration from mx6slevk. A fundamental difference between warp and mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two. The imx_ddr() function calculates the RAM size in runtime by reading the values of registers MDCTL and MDMISC. So in order to fix this warp boot issue, create a imximage DDR file specific to warp, where the MDCTL register is configured to only activates a single chip select. Reported-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Breno Lima <breno.lima@nxp.com>
| * arm: imx: Add support for Advantech DMS-BA16 boardAkshay Bhat2016-09-06-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
* | Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROLMasahiro Yamada2016-09-07-24/+0
| | | | | | | | | | | | | | | | | | | | | | If both SPL_DM and SPL_OF_CONTROL are enabled, SPL needs to bind several devices, but CONFIG_SYS_MALLOC_F_LEN=0x400 is apparently not enough. Increase the default to 0x2000 for the case. This will be helpful for shorter defconfigs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | configs: am4xhs: Modify SPL load address to fix UART boot issueMadan Srinivas2016-09-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An issue in the TI secure image generation tool causes the ROM to load the SPL at a different load address than what is specified by CONFIG_ISW_ENTRY_ADDR while doing a peripheral boot on HS devices. This causes the SPL to fail on secure devices during peripheral boot. The TI secure image generation tool has been fixed so that the SPL will always be loaded at 0x403018E0 by the ROM code for both peripheral and memory boot modes. Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: AM57xx: Enable post-processing of FIT artifacts loaded by U-BootAndreas Dannenberg2016-09-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI AM57xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7xx: Enable post-processing of FIT artifacts loaded by U-BootAndreas Dannenberg2016-09-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI DRA7xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-08-21 03:00:44 +0000