| Commit message (Collapse) | Author | Age | Lines |
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move the UBI config options into Kconfig.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andrew F. Davis <afd@ti.com>
Reviewed by: Evgeni Dobrev <evgeni at studio-punkt.com>
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This reverts commit 90c08d9e08c7a108ab904f3bbdeb558081757892.
I took a closer look at this after the commit was applied, and found
CONFIG_SYS_MALLOC_F_LEN=0x2000 was too much. 8KB memory for SPL is
actually too big for some boards. Perhaps 0x800 is enough, but the
situation varies board by board.
Let's postpone our decision until we come up with a better idea.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Move the SPL settings into common/spl where most of the SPL code is kept.
Signed-off-by: Simon Glass <sjg@chromium.org>
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move VERSION_VARIABLE from board config file into a
Kconfig option.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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If both SPL_DM and SPL_OF_CONTROL are enabled, SPL needs to bind
several devices, but CONFIG_SYS_MALLOC_F_LEN=0x400 is apparently
not enough. Increase the default to 0x2000 for the case. This
will be helpful for shorter defconfigs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This option controls how long it should be paused before entering
the auto-boot mode. The default value from Kconfig should be fine
except socfpga_vining_fpga_defconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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This recently added board missed the tree-wide migration of
CONFIG_BOOTDELAY.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
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This adds support for IS1 board. Pretty usual socfpga board,
256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two
additional ethernet ports connected to the FPGA.
Signed-off-by: Pavel Machek <pavel@denx.de>
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