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1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665)
Conflicts:
board/freescale/mx6qsabreauto/mx6qsabreauto.c
boards.cfg
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