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* cosmetic: rockchip: rk3288: pinctrl: fix config symbol namingHeiko Stübner2016-07-25-1/+1
| | | | | | | | The rk3288 pinctrl is very specific to this soc, so should not hog the generic rockchip naming. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* configs: Re-sync BOOTDELAY changesTom Rini2016-06-17-0/+1
| | | | | | | | With updated moveconfig.py and an better default, re-generate the migration of BOOTDELAY to the defconfig. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig optionHeiko Schocher2016-06-09-1/+0
| | | | | | | | | | | move CONFIG_BOOTDELAY into a Kconfig option. Used for this purpose the moveconfig.py tool in tools. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* Rename reset to sysresetStephen Warren2016-05-26-1/+1
| | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* configs: Re-sync with cmd/KconfigTom Rini2016-04-25-0/+8
| | | | | | | Update the config.h and defconfig files for the commands that 8e3c036 converted over to Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Re-sync almost all of cmd/KconfigTom Rini2016-04-25-0/+7
| | | | | | | | This syncs up the current cmd/Kconfig and include/configs/ files with the only exception being CMD_NAND. Due to how we have used this historically we need to take further care here when converting. Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Re-sync HUSH optionsTom Rini2016-04-25-0/+1
| | | | | | | Move all cases of CONFIG_SYS_HUSH_PARSER out of the config.h files. Remove all cases of CONFIG_SYS_PROMPT_HUSH_PS2 as everyone uses the default. Signed-off-by: Tom Rini <trini@konsulko.com>
* defconfig: Reorder boards' defconfig filesBin Meng2016-03-22-2/+0
| | | | | | | Some boards' defconfig files are out of order. Clean this up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* rockchip: Drop old CONFIG_VIDEO_ROTATION optionSimon Glass2016-02-06-1/+0
| | | | | | | | | | The option was renamed to CONFIG_CONSOLE_ROTATION and Rockchip boards were not updated. However this option is is not needed by default for Rockchip since we don't need a rotated console for current boards. So just remove the old option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* video: add CONFIG_I2C_EDID and disable CONFIG_DISPLAY by defaultAnatolij Gustschin2016-01-26-0/+2
| | | | | | | | | | | | | | | Enabling CONFIG_DISPLAY breaks building for some architectures (microblaze-generic), so we disable CONFIG_DISPLAY in Kconfig by default and enable this option in defconfigs. CONFIG_DISPLAY depends on CONFIG_I2C_EDID, so add and enable it in defconfigs, too. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reported-by: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* rockchip: jerry: Enable EDP and HDMI video outputSimon Glass2016-01-21-0/+6
| | | | | | | | | | | Enable these devices using the VOPL video output device. We explicitly disable VOPB in the device tree to avoid it taking over. Since this device has an LCD display this comes up by default. If the display fails for some reason then it will attempt to use HDMI. It is possible to force it to fail (and thus fall back to HDMI) by puting 'return -EPERM' at the top of rk_edp_probe(). For now there is no easy way to select between the two. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+1
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Enable the Chrome OS ECSimon Glass2016-01-21-0/+8
| | | | | | Turn on the EC and enable the keyboard. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Drop unused optionsSimon Glass2016-01-21-5/+0
| | | | | | | To reduce the SPL image size, drop the LED features. Jerry does not have an LED and we can leave out GPIO support also. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Disable simple-bus in SPL for firefly-rk3288, jerrySimon Glass2016-01-21-0/+1
| | | | | | This is not needed for booting, so drop it from SPL to save about 300 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Enable the RK808 PMIC and regulatorSimon Glass2016-01-21-0/+2
| | | | | | Enable this PMIC and regulator, which is used on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Move firefly and jerry to use the full pinctrlSimon Glass2016-01-21-1/+0
| | | | | | Use the full pinctrl driver in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Use a separate clock ID for clocksSimon Glass2016-01-21-0/+1
| | | | | | | | | | At present we use the same peripheral ID for clocks and pinctrl. While this works it is probably better to use the device tree clock binding ID for clocks. We can use the clk_get_by_index() function to find this. Update the clock drivers and the code that uses them. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Use pwrseq for MMC start-up on jerrySimon Glass2016-01-21-0/+1
| | | | | | | This is defined in the device tree in Linux. Copy over the settings so that this can be used instead of hard-coding the reset line. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Correct the defconfig orderSimon Glass2016-01-21-3/+3
| | | | | | This has got out of sequence somehow. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Fix the configuration for chromebook_jerrySimon Glass2016-01-08-0/+4
| | | | | | | | Various updates did not make it through to this board. Also the instructions for building a SPI image are no-longer correct. Fix these so that Jerry can boot to a prompt again. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Explicitly set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LENSjoerd Simons2015-12-01-0/+1
| | | | | | | | | | | | | | Now that u-boot relocates the malloc area in SPL to SDRAM, with the malloc area sitting below the SPL_STACK_R_ADDR the SPL_STACK_R_MALLOC_SIMPLE_LEN needs to be set explicitly for rockchip as its SPL_STACK_R_ADDR (512kb) is smaller then STACK_R_MALLOC_SIMPLE_LEN (1Mb). Using the same value as SYS_MALLOC_F_LEN (8kb) is enough to load u-boot from SD card. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* dm: core: Add SPL Kconfig for REGMAP and SYSCONhuang lin2015-12-01-0/+2
| | | | | | | | Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* spi: Move SPI drivers to defconfigBin Meng2015-11-25-1/+0
| | | | | | | | There are already Kconfig options for SPI drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* ns16550: move CONFIG_SYS_NS16550 to KconfigThomas Chou2015-11-21-0/+1
| | | | | | Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* rockchip: Turn on CONFIG_DEBUG_UART_NS16550 in defconfigsAriel D'Alessandro2015-11-19-0/+1
| | | | | | | | | | No UART driver was specified in defconfig, thus DEBUG_UART_ALTERA_JTAGUART was incorrectly selected by default since commit 220e8021af96741bd7149ca9895e1f0c8a38d0bb added a new Altera UART driver. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* common: add CMD_GPIO to KconfigThomas Chou2015-11-18-1/+1
| | | | | | | Add CMD_GPIO to Kconfig and run tools/moveconfig.py . Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* Reorder defconfigs with 'savedefconfig'Bin Meng2015-09-28-13/+11
| | | | | | Some boards' defconfigs are disordered. Reorder them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* rockchip: Add basic support for jerrySimon Glass2015-09-02-0/+43
This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-07 18:34:22 +0000