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* x86: gpio: Allow the pinctrl driver to set up the pin configSimon Glass2016-03-17-0/+2
| | | | | | | | Rather than setting up the pin configuration in the GPIO driver, use the new pinctrl driver to do it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* Correct defconfig orderingSimon Glass2016-03-14-2/+2
| | | | | | | | Various boards have the wrong Kconfig ordering now. To avoid a misleading diff in the next patch, reorder the configuration correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* vsprintf.c: Always enable CONFIG_SYS_VSNPRINTFTom Rini2016-01-19-1/+0
| | | | | | | | | | | | | | Enabling this function always removes some class of string saftey issues. The size change here in general is about 400 bytes and this seems a reasonable trade-off. Cc: Peng Fan <peng.fan@nxp.com> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: Convert to use driver model timerBin Meng2015-12-01-0/+1
| | | | | | | Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* sf: Move SPI flash drivers to defconfigBin Meng2015-11-25-0/+3
| | | | | | | | There are already Kconfig options for SPI flash drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* spi: Move SPI drivers to defconfigBin Meng2015-11-25-0/+1
| | | | | | | | There are already Kconfig options for SPI drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* ns16550: move CONFIG_SYS_NS16550 to KconfigThomas Chou2015-11-21-0/+1
| | | | | | Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* common: add CMD_GPIO to KconfigThomas Chou2015-11-18-0/+1
| | | | | | | Add CMD_GPIO to Kconfig and run tools/moveconfig.py . Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+1
| | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Reorder defconfigs with 'savedefconfig'Bin Meng2015-09-28-4/+4
| | | | | | Some boards' defconfigs are disordered. Reorder them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: bayleybay: Convert to use more dm driversBin Meng2015-09-09-1/+3
| | | | | | | Move to driver model for USB and ETH on Intel Bayley Bay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: bayleybay: Change default vga bios rom addressBin Meng2015-09-09-0/+1
| | | | | | | | | | With multiple microcode blobs included, the generated u-boot-dtb.bin leaves merely several hundred bytes before the vga bios. Change the vga bios rom address to make a bigger room for u-boot-dtb.bin. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* net: Move CONFIG_E1000 options to KconfigSimon Glass2015-08-21-0/+2
| | | | | | | | Move config for the E1000 Ethernet driver to Kconfig and tidy up affected boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* x86: bayleybay: Configure PCI IRQBin Meng2015-08-05-0/+2
| | | | | | | | Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Bayley Bay board supportBin Meng2015-08-05-0/+25
Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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