| Commit message (Collapse) | Author | Age | Lines |
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Signed-off-by: John Traill <john.traill@freescale.com>
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The changes works in with kernel irq mapping rework.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
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Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
With attached patch, we can use command "mac/mac read/mac save/"
to read and write EEPROM under u-boot prompt.
U-boot will calculate the checksum of EEPROM while bootup,
if it is right, then u-boot will check whether the mac address
of eTSEC0/1/2/3 is availalbe (non-zero).
If there is mac address availabe in EEPROM, u-boot will use it,
otherewise, u-boot will use the mac address defined in
MPC8641HPCN.h. This matches the requirement to set unique mac address
for each TSEC port.
Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
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Signed-off-by: Jon Loeliger <jdl@jdl.com>
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Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Some 80-column cleanups.
Convert printf() to puts() where possible.
Use #include "spd_sdram.h" as needed.
Enhanced reset command usage message a bit.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Signed-off-by: Jon Loeliger <jdl@freescale.com>
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First cut at moving the PIXIS platform code out of
the 86xx cpu directory and into board/mpc8641hpcn
where it belongs.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Updated ethernet interrupt mappings (moved up 48).
Cleaned up a few comments.
Signed-off-by: Jon Loeliger <jdl@jdl.com>
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Correctly tracks r29 as global data pointer now.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Enable the CFI driver.
Remove bogus LAWBAR7 cruft.
Use correct TEXT_BASE, Fixup load script.
Enable SPD EEPROM during DDR setup.
Use generic RFC 1918 IP addresses by default.
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Removed //-style comments.
Use 80-column lines.
Remove trailing whitespace.
Remove dead code and debug cruft.
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(and then only if PSC6_3 is read as "1" when booting).
Patch by Martin Krause, 21 Jun 2006
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Based on patch by Mike Frysinger, 20 Jun 2006
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Patch by Aaron Sells, 20 Jun 2006
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- Map in a additional chip selects CS4 and CS5.
- Modify the port configration, configure six UARTs and no PCI,
ATA and USB.
- Add custom flash driver to handle specific byte swapping
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Patch by Stefan Roese, 30 Sep 2006
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Patch by Stefan Roese, 23 Sep 2006
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Patch by Stefan Roese, 13 Sep 2006
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(according to S1 switch setting).
Patch by Marian Balakowicz, 12 Sep 2006
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Patch by Stefan Roese, 12 Sep 2006
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- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
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