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* Merge branch 'master' of git://88.191.163.10/u-boot-armTom Rini2013-08-18-1226/+2106
|\ | | | | | | | | | | | | | | | | | | Fixup an easy conflict over adding the clk_get prototype and USB_OTG defines for am33xx having moved. Conflicts: arch/arm/include/asm/arch-am33xx/hardware.h Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-08-17-939/+75
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| | * Merge git://git.denx.de/u-boot-armStefano Babic2013-07-31-37124/+3245
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mx6qsabrelite/Makefile board/freescale/mx6qsabrelite/mx6qsabrelite.c include/configs/mx6qsabrelite.h Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | imx: nitrogen6x: mx6qsabrelite: Add support for DVI monitorsRobert Winkler2013-07-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A little background is probably appropriate for this patch. Since "the beginning" of usage of the SABRE Lite and Nitrogen6x boards, DVI detection has been somewhat broken. Some (most) DVI monitors don't produce the "HPD" bit in the PHY_STAT0 register, but do show proper toggling of the RX_SENSE0..3 bits. Creating a new the bit-mask to include all five bits and modifying the 'hdmidet' command and internal detection routines allows these monitors to function properly in U-Boot. A related patch to our kernels allows things to work under Linux: https://github.com/boundarydevices/linux-imx6/commit/7d8752905c118af9063738a533227de0b2f6ecd4 Signed-off-by: Robert Winkler <robert.winkler@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | mx6qsabresd: Add splash screen support via HDMIPardeep Kumar Singla2013-07-27-1/+63
| | | | | | | | | | | | | | | | Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
| | * | mx6: Factor out common HDMI setup codePardeep Kumar Singla2013-07-27-77/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of duplicating HDMI setup code for every mx6 board, factor out the common code Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com> Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
| | * | mx6qsabrelite: Remove mx6qsabrelite code in favor of nitrogen6xFabio Estevam2013-07-26-889/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6qsabrelite and nitrogen6q boards are hardware compatible, so let's avoid the code duplication and only use the nitrogen6x source code to make board code maintainance easier. Tested booting a mainline device tree kernel on a mx6qsabrelite board. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | Add TI816X evm board supportTENART Antoine2013-08-15-0/+266
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Change to SPDX, fix a few compiler warnings, adapt to CONFIG_OMAP_COMMON] Signed-off-by: Tom Rini <trini@ti.com>
| * | | arm, da850: add ipam390 board supportHeiko Schocher2013-08-15-0/+861
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add the am1808 based ipam390 board from Barix. - 128MByte, DDR2, synchronous RAM 16bit databus to SDRAM interface - 128MByte, NAND Flash, 8bit databus to the NANDFlash Interface - Ethernet PHY Micrel KSZ8051R via RMII - Console on UART 0 - booting fron nand flash - spl falcon bootmode Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
| * | | am33xx: Stop using PHYS_DRAM_1 defineTom Rini2013-08-15-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We defined PHYS_DRAM_1 to 0x80000000 (start of DRAM) and then used this for CONFIG_SYS_SDRAM_BASE. But then we kept on referencing PHYS_DRAM_1 in other places. Change to directly setting CONFIG_SYS_DRAM_BASE and then using that name in code. Signed-off-by: Tom Rini <trini@ti.com>
| * | | OMAP3: igep00x0: allow booting with a FDT from MMCJavier Martinez Canillas2013-08-15-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IGEP boards now have Device Tree support in the mainline kernel. To boot an IGEP board using a DT, a uEnv.txt plain text file could be used to define a custom uenvcmd that will be run by the default boot command. It is more convenient to change the default boot command to allow loading a FDT if it is stored in the boot dir of the rootfs uSD/MMC partition. If no FDT is found then the defaul command tries to boot a zImage without a DT using legacy boot. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
| * | | omap: overo: Use 200MHz SDRC timings for revision 1, 2 & 3 boardsAsh Charles2013-08-15-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Gumstix uses 200Mhz RAM on revision 1, 2 & 3 COMs, so use 200MHz timings rather than 165MHz. Based on 6cf8bf44b1f8550e12f7f2a16e01890e5de8443d Signed-off-by: Ash Charles <ashcharles@gmail.com>
| * | | omap: overo: update support for Micron 1GB POPSteve Sakoman2013-08-15-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: Ash Charles <ashcharles@gmail.com>
| * | | ARM: IGEP0033: Remove CYGNUS name from header.Enric Balletbo i Serra2013-08-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will not use CYGNUS names for any IGEP COM based on AM335x processor, so, to avoid confusion, remove from headers. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
| * | | ARM: AM43xx: clocks: Add dpll and clock dataLokesh Vutla2013-08-15-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: AM43xx: Add Board filesLokesh Vutla2013-08-15-0/+138
| | | | | | | | | | | | | | | | | | | | | | | | Add board specific information for AM43xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: AM33xx: Move s_init to a common placeHeiko Schocher2013-08-15-208/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | ARM: AM33xx: Cleanup clocks layerLokesh Vutla2013-08-15-17/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleaning up the clocks layer. This helps in addition of new Soc with minimal changes. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | ARM: AM33xx: Cleanup dplls dataLokesh Vutla2013-08-15-0/+46
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | gpio: omap5-uevm: Configure the tca6424 gpio expanderDan Murphy2013-07-30-0/+24
| | | | | | | | | | | | | | | | | | | | | Configure the tca6424 gpio expander This allows use of the debug and tri color LEDs. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | board/ti/am335x/README: Document NOR programmingTom Rini2013-07-30-0/+23
| | | | | | | | | | | | | | | | | | | | | The Beaglebone White may be populated with a memory cape that has a NOR module. Document how to program it. Signed-off-by: Tom Rini <trini@ti.com>
| * | am335x_evm: Add support to boot from NOR.Steve Kipisz2013-07-30-7/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c with TI81xx checks as at this time U-Boot does not discard unused sections in the main build and this code relies on functions specific to (and only provided in) ti81xx-related code. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | am335x_evm: Add support for the NOR module on the memory capeSteve Kipisz2013-07-30-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Clean up config changes slightly] Signed-off-by: Tom Rini <trini@ti.com>
| * | am335x_evm: Rework board_is_foo() checksTom Rini2013-07-30-58/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We rework the various board_is_foo() checks to take a pointer to struct am335x_baseboard_id rather than using a local copy in board.c. This allows us to make use of the same checks in mux.c as well as fixing problems when this code could be running from read-only memory. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
| * | board/ti/am335x/README: Document NAND programmingTom Rini2013-07-30-0/+24
| | | | | | | | | | | | | | | | | | | | | The AM335x GP EVM ships with NAND. Document programming of the chip including the redundant locations that the ROM will check. Signed-off-by: Tom Rini <trini@ti.com>
| * | beagleboard: remove RevB support for BeagleBoard XmNishanth Menon2013-07-26-23/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported in http://marc.info/?l=u-boot&m=137358037827735&w=2 There is no need for the "xMB" variant, as the gpio pins used for identification where never changed from the xMA when the newer silcon was used for the xMB, So rename XM A revision as AB revision and report accordingly Reported-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| * | ARM: DRA7xx: Add CPSW and MDIO pinmux supportMugunthan V N2013-07-26-0/+14
| | | | | | | | | | | | | | | | | | Adding CPSW Slave 0 and MDIO pinmux support for DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | ARM: DRA7xx: Add CPSW support to DRA7xx EVMMugunthan V N2013-07-26-5/+145
| | | | | | | | | | | | | | | | | | Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | drivers: net: cpsw: remove hard coding bd ram for cpswMugunthan V N2013-07-26-0/+2
| | | | | | | | | | | | | | | | | | | | | BD ram address may vary in various SOC, so removing the hardcoding and passing the same information through platform data Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | am335x_evm: Add basic READMETom Rini2013-07-26-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a README for the family of boards the am335x_evm covers, and include instructions on preparing and using falcon mode, for various media. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | da850evm: Use clrbits function with correct endianessChristian Riesch2013-07-26-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code uses clrbits_be32 which is incorrect since we are on a little endian machine here. This patch fixes this issue and also removes some unnecessary code: Reading the current GPIO bank state is not required if we are using the SET and CLEAR GPIO registers for setting/clearing bits. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
| * | Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD2013-07-25-37021/+2552
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| * | | socfpga: Move board/socfpga_cyclone5 to board/socfpgaDinh Nguyen2013-07-25-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the SOCFPGA platform will include support for Cyclone V and Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to be more generic. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> v2: - Add Reviewed-by: Pavel Machek - Cc: Tom Rini
| * | | ARM: highbank: compile misc_init_r only if CONFIG_MISC_INIT_RRob Herring2013-07-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Compile misc_init_r only if CONFIG_MISC_INIT_R is enabled. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | ARM: highbank: setup peripherals based on power domain statusRob Herring2013-07-25-2/+29
| | |/ | |/| | | | | | | | | | | | | | | | | | | Accessing powered down peripherals will hang the bus, so check power domain status before initializing SATA and fixup the FDT to disable unused peripherals. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | | powerpc/c29xpcie: add readme document for c29xpciePo Liu2013-08-14-0/+100
| | | | | | | | | | | | Signed-off-by: Po Liu <Po.Liu@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-13-174/+1730
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| * | | powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-12-177/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/c29xpcie: add support for C29XPCIE boardMingkai Hu2013-08-09-0/+552
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Singed-off-by: Po Liu <Po.Liu@freescale.com> [yorksun: Fixup include/configs/C29XPCIE.h] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | board/b4860qds: Add support for configuring SerDes1 RefclksShaveta Leekha2013-08-09-2/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | board/freescale/common: IDT8T49N222A configuration codeShaveta Leekha2013-08-09-0/+341
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code for configuring IDT8T49N222A device for various output refclks - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with alarm and monitoring functions suitable for networking and communications applications. It is able to generate wide range of output frequencies. - In B4860QDS, it has been used to generate different refclks to SerDes modules - Programming of these devices are performed by I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | board/bsc9132qds: Configure DSP DDR controllerPriyanka Jain2013-08-09-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | board/bsc9132qds: Add DSP side tlb and lawsPriyanka Jain2013-08-09-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | p1020rdb-pd: platform supportHaijun.Zhang2013-08-09-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB. DDR changed from DDR2 1G to DDR3 2G. NAND: 128 MiB Flash: 64 MiB Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t4240qds: Adjust DDR timing for RDIMMYork Sun2013-08-09-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for dual rank. Single- and quad-rank are not tested due to availability. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/T4240EMU: Add T4240EMU targetYork Sun2013-08-09-105/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/corenet: Move RCW print to cpu.cYork Sun2013-08-09-58/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/85xx: Add TWR-P10xx board supportXie Xiaobo2013-08-09-0/+544
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TWR-P1025 Specification: ----------------------- Memory subsystem: 512MB DDR3 (on board DDR) 64Mbyte 16bit NOR flash One microSD Card slot Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC3: Connected to Atheros AR8035 GETH PHY UART: Two UARTs are routed to the FDTI dual USB to RS232 convertor USB: Two USB2.0 Type A ports I2C: AT24C01B 1K Board EEPROM (8 bit address) QUICC Engine: Connected to DP83849i PHY supply two 10/100M ethernet ports QE UART for RS485 or RS232 PCIE: One mini-PCIE slot Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [yorksun: Fixup include/configs/p1_twr.h] Signed-off-by: York Sun <yorksun@freescale.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-videoTom Rini2013-08-12-2/+26
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