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| * | | T4240/ramboot: enable PBL tool for T4240Shaohui Xie2013-05-24-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/t4240qds: Add VDD overrideYork Sun2013-05-24-2/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/t4240qds: Add board detail for bdinfo commandYork Sun2013-05-24-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print more detail information including core voltage, RCW source, switch settings, etc. with bdinfo command. Signed-off-by: York Sun <yorksun@freescale.com> CC: Wolfgang Denk <wd@denx.de> CC: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-97/+626
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| | * | | T4240/eth: fix SGMII card PHY addressShaohui Xie2013-05-14-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card assumed to be used by default, but if SGMII card is used, it will use different PHY address, but we don't know which card is used until we access PHY on the card. So we check the card type slot by slot, if we can read a PHY ID by reading a SGMII PHY address on a slot, then the slot must have a SGMII card pluged, we mark all ports on that slot, and fix dts to use the SGMII card PHY address when doing dts fixup for the marked ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/t4qds: Fix disabling remote I2C connectionEd Swarthout2013-05-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/b4860qds: Assign DDR address in board fileYork Sun2013-05-14-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | T4240/net: use QSGMII card PHY address by defaultShaohui Xie2013-05-14-56/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-14-14/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/t4240qds: Add voltage ID supportYork Sun2013-05-14-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | powerpc/t4240qds: Update DDR timing tableYork Sun2013-05-14-22/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | | T4/serdes: fix the serdes clock frequencyRoy Zang2013-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-1736/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
| * | | | blackfin: bf609: add softswitch config commandBob Liu2013-05-13-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add softswitch_output command for bf609-ezkit to enable softswitches. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | | | blackfin: bf609: implement soft switchSonic Zhang2013-05-13-0/+251
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up soft switch pins properly in board init code. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Scott Jiang <scott.jiang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
| * | | openrisc: move board linker script(s) to a common in cpu/Stefan Kristiansson2013-05-10-77/+0
| | | | | | | | | | | | | | | | | | | | | | | | Unifies the openrisc boards linker scripts into a common one. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
| * | | openrisc: specify a memory region for u_boot_listsStefan Kristiansson2013-05-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since there are two memory areas defined, vectors and ram, the linker will error when neither of them are specified for a section. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
| * | | Fix references to the documentation filesAnatolij Gustschin2013-05-10-42/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boot image configuration files refer to the appropriate documentation file, but these references contain typos in the directory and file name. Fix them. Also fix reference to doc/README.SPL file. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | gpio: Add support for microblaze xilinx GPIOMichal Simek2013-05-09-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microblaze uses gpio which is connected to the system reset. Currently gpio subsystem wasn't used for it. Add gpio driver and change Microblaze reset logic to be done via gpio subsystem. There are various configurations which Microblaze can have that's why gpio_alloc/gpio_alloc_dual(for dual channel) function has been introduced and gpio can be allocated dynamically. Adding several gpios IP is also possible and supported. For listing gpio configuration please use "gpio status" command This patch also remove one compilation warning: microblaze-generic.c: In function 'do_reset': microblaze-generic.c:38:47: warning: operation on '*1073741824u' may be undefined [-Wsequence-point] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Tegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhuTom Warren2013-05-28-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both board and board_name == beaver. Didn't test as I have no T30 Beaver board here. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | | | ARM: Add Seagate GoFlex Home supportSuriyan Ramasami2013-05-23-0/+408
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Seagate GoFlex Home support Start with dockstar configuration define support for RTC, DATE, SATA and EXT4FS Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
* | | | ARM: vexpress: create A5 specific board configRyan Harkin2013-05-23-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates a new config for the A5 dual core tile that includes the generic config for the Versatile Express platform. The generic config has been modified to provide support for the Extended Memory Map, as used on the A5 core tile. A5 does not support the legacy memory map. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | | | ARM: vexpress: refactoring of Versatile Express CA9x4 supportRyan Harkin2013-05-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ca9x4_ct_vxp platform contains support for a Versatile Express motherboard with a quad core A9 core tile. This patch separates the Versatile Express motherboard code and the A9 specific code, to ease supporting more core tiles in the next patches. Andre: merged the first two of Ryan's original patches and did some checkpatch fixes. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | | | ARM: atmel: add sama5d3xek supportBo Shen2013-05-21-0/+326
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sama5d3xek support with following feature - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector - boot from SPI flash support - boot from SD card support - LCD support - EMAC support - USB OHCI support Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | at91sam9260ek: move board id setup to config headerAndreas Bießmann2013-05-12-12/+0
| | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Bo Shen <voice.shen@atmel.com>
* | | arm: at91: enable mci support for at91sam9g20ek.Wu, Josh2013-05-12-0/+10
| | | | | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: add at91sam9n12ek board supportWu, Josh2013-05-12-0/+280
| |/ |/| | | | | | | | | | | | | | | | | | | | | Add support for following features: - nand boot, with PMECC 2bit ECC for 512 bytes sector - SPI flash boot - SD card boot - LCD support Signed-off-by: Josh Wu <josh.wu@atmel.com> [fix -Wimplicit-function-declaration for at91_lcd_hw_init()] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-54/+568
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| * | cm-t35: move cm-t35 to live in compulab directoryIgor Grinberg2013-05-10-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the cm-t35 support code lives under board/cm_t35 directory. Some of the code can be shared with other/future CompuLab boards, so move the cm-t35 to live under board/compulab/cm_t35 directory. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | ARM:Panda:Fix device tree loading for the panda-esDan Murphy2013-05-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the device tree loading for panda(4430) and panda-es(4460) Modify the board name if a 4460 panda or panda-es is detected at run time. In the findfdt add a check for the panda-es board name and load the panda-es device tree blob. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: Add support for IGEP COM AQUILA/CYGNUSEnric Balletbo i Serra2013-05-10-0/+394
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IGEP COM AQUILA and CYGNUS are industrial processors modules with following highlights: o AM3352/AM3354 Texas Instruments processor o Cortex-A8 ARM CPU o 3.3 volts Inputs / Outputs use industrial o 256 MB DDR3 SDRAM / 128 Megabytes FLASH o MicroSD card reader on-board o Ethernet controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
| * | beagleboard: Update comment in get_board_rev()Tom Rini2013-05-10-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | We are able to tell the difference between xM Rev Ax/Bx and xM Rev Cx, and have been for some time. The comment above the function however did not list this, so update. Signed-off-by: Tom Rini <trini@ti.com>
| * | palmas: rename init_settings to an generic palmas initNishanth Menon2013-05-10-1/+1
| | | | | | | | | | | | | | | | | | | | | Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs, rename twl6035_init_settings with an more generic palmas_init_settings Signed-off-by: Nishanth Menon <nm@ti.com>
| * | twl6035: rename to palmasNishanth Menon2013-05-10-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs Rename twl6035 to palmas to allow reuse across multiple current and future platforms As part of this change, change the CONFIG_TWL6035_POWER to CONFIG_PALMAS_POWER and update usage of header file accordingly. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | twl4030: make twl4030_i2c_read_u8 prototype consistentNishanth Menon2013-05-10-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot standard i2c read prototype is i2c_read(addr, reg, 1, &buf, 1) twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val) Signed-off-by: Nishanth Menon <nm@ti.com>
| * | twl4030: make twl4030_i2c_write_u8 prototype consistentNishanth Menon2013-05-10-29/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot standard i2c register write prototype is i2c_reg_write(u8 addr, u8 reg, u8 val) twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val) Signed-off-by: Nishanth Menon <nm@ti.com>
| * | ti814x_evm: enable CPSW supportMatt Porter2013-05-10-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | Adds CPSW support to the TI814X EVM configured with an ET1011C PHY in GMII mode. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | am33xx: add pll and clock support for TI814x CPSWMatt Porter2013-05-10-0/+3
| | | | | | | | | | | | | | | | | | | | | Enables required PLLs and clocks for CPSW on TI814x. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-1966/+2720
|\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
| * | | imx: mx35pdk: Fix MUX2_CTR GPIOBenoît Thébaudeau2013-05-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MUX2_CTR is on GPIO1[5], not GPIO2[5], and it needs to be set high in order to connect the FEC. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | mx23_olinuxino: Do not set voltage selection bit for SSP padsFabio Estevam2013-05-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | mx23 SSP pad registers do not contain voltage selection bit, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx23evk: Do not set voltage selection bit for SSP padsFabio Estevam2013-05-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | mx23 SSP pad registers do not contain voltage selection bit, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | imx: m53evk: Convert to iomux-v3Benoît Thébaudeau2013-05-05-200/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior, except for the folloing line that has been removed because the iomux mode was not set accordingly and the pad used for OTG OC is not this one: mxc_iomux_set_input(MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, 1); Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | imx: mx53smd: Convert to iomux-v3Benoît Thébaudeau2013-05-05-104/+48
| | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | imx: mx53loco: Convert to iomux-v3Benoît Thébaudeau2013-05-05-223/+113
| | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | imx: mx53evk: Convert to iomux-v3Benoît Thébaudeau2013-05-05-206/+83
| | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | imx: mx53ard: Convert to iomux-v3Benoît Thébaudeau2013-05-05-186/+141
| | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | imx: ima3-mx53: Convert to iomux-v3Benoît Thébaudeau2013-05-05-155/+73
| | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | imx: vision2: Convert to iomux-v3Benoît Thébaudeau2013-05-05-362/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior, except for older silicon revisions for which support is removed. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | imx: mx51_efikamx/sb: Convert to iomux-v3Benoît Thébaudeau2013-05-05-53/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no change of behavior, except for older silicon revisions for which support is removed. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Matt Sealey <matt@genesi-usa.com>
generated by cgit v1.1 at 2024-11-07 16:26:38 +0000