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* colibri_t20: disable PMIC sleep mode on low supply voltageMarcel Ziswiler2015-08-13-0/+35
| | | | | | | | | | | | | | | | | | The Colibri T20's PMIC enters a sleep mode on low supply voltage < 3.0V ±2.5% (2.92...3.08V). Rising the main supply voltage again does not bring it back to regular operation. Not even a full reset does bring the module back. A full power cycle was required to reboot the system. A long positive pulse on the PMICs resume pin also reboots the system but this pin is only accessible as a test point on the module. This patch configures the PMIC through I2C to not enter this sleep mode plus force it to normal state upon sleep request exit should this ever happen. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* colibri_t20: add lcd display supportMarcel Ziswiler2015-08-13-0/+18
| | | | | | | | | | Add LCD display support defaulting to VESA VGA resolution. Different resolutions configurable via device tree. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* apalis/colibri_t20/t30: integrate recovery mode detectionMarcel Ziswiler2015-08-13-0/+36
| | | | | | | | | | | | Allow detecting whether or not U-Boot was launched through the recovery mode of the resp. NVIDIA SoC. Make use of a board specific arch_misc_init() and enable the same via CONFIG_ARCH_MISC_INIT configuration option. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dra7xx: Move CONS_INDEX to Kconfig and enable CONFIG_SPL_STACK_ADDRTom Rini2015-08-12-0/+8
| | | | | | | | - Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and into Kconfig proper. - While in here, enable CONFIG_SPL_STACK_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: am437x: Introduce new board cm-t43Nikita Kiryanov2015-08-12-0/+457
| | | | | | | | | | | Add initial support for CM-T43, an AM437x based SoM. This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM detection. Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* ARM64: hikey: Add a README for this board.Peter Griffin2015-08-12-0/+160
| | | | | | | To help others with compiling and flashing ATF and u-boot add a README for this board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board.Peter Griffin2015-08-12-0/+379
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's. This initial port adds support for: - 1) Serial 2) eMMC / SD card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Notes: eMMC has been tested with basic reading of eMMC partition into DDR. I have not tested writing / erasing. Due to lack of clock control it won't be running in the most performant high speed mode. SD card slot has been tested for reading and booting kernels into DDR. It is also currently configured to save the u-boot environment to the SD card. USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage are correctly enumerated. GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs. Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* ARM: keystone2: Remove unsed external clocksLokesh Vutla2015-08-12-16/+2
| | | | | | | | Remove unused external clocks and make a common definition for all keystone platforms. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Cleanup init_pll definitionLokesh Vutla2015-08-12-41/+74
| | | | | | | | | This is just a cosmetic change that makes the calling of pll init code looks much cleaner. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Fix dev and arm speed detectionLokesh Vutla2015-08-12-26/+42
| | | | | | | | | Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Cleanup PLL init codeLokesh Vutla2015-08-12-1/+12
| | | | | | | | | | | There are two types of PLL for all keystone platforms: Main PLL, Secondary PLL. Instead of duplicating the same definition for each secondary PLL, have a common function which does initialization for both PLLs. And also add proper register definitions. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* integrator: switch to DM serial portLinus Walleij2015-08-12-0/+18
| | | | | | | | This switches the Integrator boards over to using the device model for its serial ports. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: bcm283x: Allocate all mailbox buffers cacheline alignedAlexander Stein2015-08-12-5/+5
| | | | | | | | | | The mailbox buffer is required to be at least 16 bytes aligned, but for cache invalidation and/or flush it needs to be cacheline aligned. Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* sniper: Keypad support, with recovery and fastboot key combinationsPaul Kocialkowski2015-08-12-0/+16
| | | | | | | | | | | Using the twl4030 keypad allows booting directly into some special boot modes, such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while the VOL- key will trigger a boot to fastboot. The G (gesture) key remains unused at this point. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sniper: Power off when the power on reason is not a valid onePaul Kocialkowski2015-08-12-0/+18
| | | | | | | | | | | | | | | | In most cases, userspace will attempt to power off the device with HALT instead of POWER_OFF, which triggers a reset instead of a proper power off from the TWL4030. Hence, it is up to the bootloader to actually turn the device off when there is no reason to turn it on. A reboot identified with the OMAP reboot mode bits set is acceptable, as well as a power on reason from either the power button, USB or charger plug. Other cases should trigger a power off. Note that for the U-Boot reset command to take effect, we have to fill-in the OMAP reboot bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sniper: Power button reset supportPaul Kocialkowski2015-08-12-0/+4
| | | | | | | This adds support for resetting the device on a long press on the power button. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sniper: Fastboot supportPaul Kocialkowski2015-08-12-0/+30
| | | | | | | | | | This adds support for the fastboot USB gadget, including flashing to the internal MMC and reboot to bootloader or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Update to use Kconfig for MUSB] Signed-off-by: Tom Rini <trini@konsulko.com>
* sniper: Pass serial number through ATAGPaul Kocialkowski2015-08-12-0/+18
| | | | | | | | | Now that the serial number is correctly defined, we can pass it to the kernel using the (legacy) ATAG method. It will be automatically passed via device-tree when enabled. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sniper: Serial number support, obtained from die IDPaul Kocialkowski2015-08-12-0/+13
| | | | | | | The OMAP3 has some die-specific ID bits that we can use to give the device a (more or less) unique serial number. This is particularly useful for e.g. USB. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* sniper: OMAP3 reboot mode supportPaul Kocialkowski2015-08-12-0/+18
| | | | | | | | | This adds support for the omap3 reboot mode mechanism and exports the reboot mode via an environment variable, that is used in the boot command to make it possible to boot from the recovery partition. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* LG Optimus Black (P970) codename sniper supportPaul Kocialkowski2015-08-12-0/+477
| | | | | | | | | | | | | | | | | | | | The LG Optimus Black (P970) codename sniper is a smartphone that was designed and manufactured by LG Electronics (LGE) and released back in 2011. It is using an OMAP3630 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. This port is aimed at running an Android version such as Replicant, the fully free Android distribution. However, support for upstream Linux with device-tree and common GNU/Linux distros boot commands could be added in the future. For more information about the journey to freeing this device, please read the series of blog posts at: http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add CONFIG_OF_SUPPORT] Signed-off-by: Tom Rini <trini@konsulko.com>
* lpc32xx: devkit3250: add spl build supportVladimir Zapolskiy2015-08-12-0/+69
| | | | | | | | | | | | The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND. All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: devkit3250: update of board configurationVladimir Zapolskiy2015-08-12-1/+30
| | | | | | | | | | | | This change adds more peripherals to Timll DevKit3250 board, namely MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C. Also the default serial console is changed to UART5, added an option to pass device tree blob by means of bootm, predefined environment variables are slightly extended and reserved space on NAND to store user defined U-boot environment. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* arm: bcmcygnus: Enable Ethernet supportJiandong Zheng2015-08-12-0/+11
| | | | | | | | Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* arm, at91: support for sam9260 based smartweb boardHeiko Schocher2015-08-12-0/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for the at91sam9260 based board smartweb from siemens. SPL is used without serial support, as this SoC has only 4k sram for running SPL. Here a U-Boot bootlog: RomBOOT > U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200) CPU: AT91SAM9260 Crystal frequency: 18.432 MHz CPU clock : 198.656 MHz Master clock : 99.328 MHz Watchdog enabled DRAM: 64 MiB WARNING: Caches not enabled NAND: 256 MiB In: serial Out: serial Err: serial Net: macb0 Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Heiko Schocher <hs@denx.de>
* ARM: highbank: remove DRAM bank setupRob Herring2015-08-12-6/+0
| | | | | | | | | | | On the highbank platform the SoC's management controller firmware will probe the DRAM modules and populates the initial device tree with the correct values. Therefore the memory sizes in the DT are already correct, so remove U-Boot's DRAM bank setup so the memory node is not "fixed up" by u-boot. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* fsl: common: pfuze: no use original pfuze code if DM_PMICPeng Fan2015-08-12-0/+2
| | | | | | | | | | | | If enable DM PMIC and REGULATOR, we should not use original power framework. So need to comment out the pfuze code for original power framework, when CONFIG_DM_PMIC_PFUZE100 defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-08-0/+34
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| * sunxi: display: Add composite video out supportHans de Goede2015-08-08-0/+7
| | | | | | | | | | | | | | | | | | | | Add composite video out support. This only gets enabled on the Mele M3 for now, since that is were it was tested. It will be enabled on more boards after testing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: nand: Add pinmux and clock settings for NAND supportKarol Gugala2015-08-08-0/+27
| | | | | | | | | | | | | | | | | | | | To enable NAND flash in sunxi SPL, pins 0-6, 8-22 and 24 on port C are configured. Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKSDinh Nguyen2015-08-08-0/+1
| | | | | | | | | | | | | | | | | | Fix build error for socfpga_cyclone5_defconfig: board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function) make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1 Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut2015-08-08-0/+21
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_misc_config to wrap the remaining misc configuration values in board file. Again, introduce a function, socfpga_get_sdram_misc_config(), which returns this the structure. This is almost the final step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut2015-08-08-0/+23
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_io_config to wrap the IO configuration values in board file. Introduce socfpga_get_sdram_io_config() function, which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut2015-08-08-0/+72
| | | | | | | | | | | | | | | | | | | | | | Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager configuration values in board file. Introduce a complementary function, socfpga_get_sdram_rwmgr_config(), which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_initMarek Vasut2015-08-08-0/+15
| | | | | | | | | | | | | | | | | | | | Introduce two wrapper functions, socfpga_get_seq_ac_init() and socfpga_get_seq_inst_init() to avoid direct inclusion of the sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS generated files. This reduces namespace pollution again. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sequencer: Move qts-generated files to board dirMarek Vasut2015-08-08-0/+601
| | | | | | | | | | | | | | | | Move the files generated by QTS into the board directory, they should not be part of the driver files at all. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ddr: altera: sdram: Introduce socfpga_sdram_get_config()Marek Vasut2015-08-08-1/+187
| | | | | | | | | | | | | | | | | | | | Introduce socfpga_sdram_get_config() function implement in a board file, which returns the socfpga_sdram_config structure. This is the last step in cleaning up the socfpga_mmr_init_full(), but not the last step which allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-8/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-1/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: Move sdram_config.h to board dirMarek Vasut2015-08-08-0/+100
| | | | | | | | | | | | | | This file is absolutelly positively board specific, so move it into the correct place. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: Move generated files into qts subdirMarek Vasut2015-08-08-1/+8
|/ | | | | | | | | Move all the files generated by Quartus into the qts/ subdir of the board/altera/socfpga dir to make them explicitly separate from the generic U-Boot code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-466/+390
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| * exynos: Add support for springSimon Glass2015-08-05-0/+19
| | | | | | | | | | | | | | | | | | | | Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5250-specific board codeSimon Glass2015-08-05-310/+0
| | | | | | | | | | | | | | Now that most exynos5250 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5420-specific board codeSimon Glass2015-08-05-147/+0
| | | | | | | | | | | | | | | | Now that exynos5420 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: Remove unneeded device tree control #ifdefsSimon Glass2015-08-05-9/+8
| | | | | | | | | | | | | | Since device tree is used for all exynos5 boards, we can remove the #ifdef and reduce confusion. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Enable new features for exynos5 boardsSimon Glass2015-08-05-1/+1
| | | | | | | | | | | | | | Enable PMICs, regulators and the like so that new drivers will be made available. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Add common board code for exynos5 boards that use device treeSimon Glass2015-08-05-0/+363
| | | | | | | | | | | | | | | | | | | | Some boards use device tree for almost all board-specific configuration. They therefore do not need their own separate board code, but can all use the same version. Add a common version of the board code. It uses the PMIC, regulator and video bridge uclasses. This will support smdk5250, smdk5420, snow, spring, pit and pi. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra: Add p2371-0000 boardStephen Warren2015-08-06-0/+345
| | | | | | | | | | | | | | | | | | | | | | P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-10 07:02:30 +0000