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| * | imx: ventana: enable precharge power-down fast-exit modeTim Harvey2015-04-22-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable fast-exit precharge mode necessary for some DDR3 devices being used on Ventana boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | imx: ventana: add usb_pcisel hwconfig supportTim Harvey2015-04-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | The GW52xx has a MUX that can direct front-panel USB OTG to one of the miniPCIe sockets (for use with a cellular modem for example). Use hwconfig to steer this. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | imx: ventana: remove unused GPIO configurationTim Harvey2015-04-22-2/+0
| | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | imx: ventana: assign default ethprime dynamicallyTim Harvey2015-04-22-0/+9
| | | | | | | | | | | | | | | | | | | | | Gateworks Ventana boards don't all use IMX6 FEC, so lets define default ethprime based off the first detected device. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | imx: ventana: add i210 supportTim Harvey2015-04-22-0/+4
| | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | mx6: Add initial SPL support for HummingBoard-i2eXFabio Estevam2015-04-22-0/+381
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the initial SPL support for HummingBoard-i2eX, which is based on a MX6 Dual. For more information about HummingBoard, please check: http://www.solid-run.com/products/hummingboard/ Based on the work from Jon Nettleton and Rabeeh Khoury. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-24-70/+2067
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| * | | armv8/ls2085ardb: Enable NAND SPL supportScott Wood2015-04-23-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | freescale/qixis: Add support for booting from NANDScott Wood2015-04-23-10/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use "qixis_reset nand" to reset the board to boot from NAND. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-23-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | board/ls2085qds: Add support ethernetPrabhakar Kushwaha2015-04-23-13/+385
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of ethernet: - eth.c: mapping lane to slot for (0x2A, 0x07) - ls2085a.c: To enable/disable dpmac and get link type Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls2085ardb: Add support of LS2085ARDB platformYork Sun2015-04-23-0/+693
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun2015-04-23-0/+757
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * | | fsl-lsch3: Introduce place for common early SoC initScott Wood2015-04-23-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls2085a: Add support for reset requestpankaj chauhan2015-04-23-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls2085a: Fix generic timer clock sourceYork Sun2015-04-23-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
| * | | driver/fsl-mc: Add support of MC FlibsPrabhakar Kushwaha2015-04-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8/fsl-lsch3: Add Freescale Debug Server driverBhupesh Sharma2015-04-21-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | QE/DeepSleep: add QE deepsleep support for armZhao Qiang2015-04-21-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | QE/DeepSleep: add QE deepsleep support for mpc85xxZhao Qiang2015-04-21-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | pci/layerscape: remove unnecessary pcie_layerscape.hMinghuan Lian2015-04-21-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | Add bootscript support to esbc_validate.gaurav rana2015-04-21-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls102xa: ddr4: Use LPUART as console output to verify DCU driverAlison Wang2015-04-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On QDS board with DDR4 DIMM, LPUART is used as console output to verify DCU driver. This patch adds ls1021aqds_ddr4_nor_lpuart_defconfig for this support. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls1021atwr: add hwconfig setting to do pin muxYao Yuan2015-04-21-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale LS1021ATWR share some pins. Hwconfig option is used to allows users to choose the pin functions. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> [York Sun: revised commit message] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm/ls102xa:Add support of conditional workaround implementation as per SoC verAlison Wang2015-04-21-26/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | colibri_vf: Enable USB support for Colibri VybridSanchayan Maity2015-04-23-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable USB support on Toradex Colibri Vybrid Modules. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | | | ARM: vf610: Initial integration for Colibri VF50/VF61Sanchayan Maity2015-04-23-0/+409
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>
* | | | ARM: vf610: Enable external 32KHz oscillatorStefan Agner2015-04-23-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the SCSC (Slow Clock Source Controller) and select the external 32KHz oscillator. This improves the accuracy of the RTC. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | | | ARM: vf610: Move DDR3 initialization to imx-commonSanchayan Maity2015-04-23-229/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid code duplication, move the DDR3 initialization to the common place under imx-common. Currently ROW_DIFF and COL_DIFF can be chosen from the board file. The JEDEC timings are specified using a common ddr3_jedec_timings structure. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | | | m68k: add architecture-specific u-boot.ldsangelo@sysam.it2015-04-23-1780/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add architecture-specific u-boot.lds and remove all board-specific u-boot.lds. All the .text customization that was board-specific have been moved inside the related include/configs, inside a LDS_BOARD_TEXT define. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | | | ARM: DRA7: Set serial number environment variableDileep Katta2015-04-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch populates serial number environment variable from die_id_0 and die_id_1 register values for DRA7xx boards. The function is added in omap common code so that this can be re-used. Serial# environment variable will be useful to show correct information in "fastboot devices" commands. Ref: http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=a6bcaaf67f6e4bcd97808f53d0ceb4b0c04d583c Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | davinci: add support for omapl138-lcdk boardPeter Howard2015-04-23-0/+431
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Peter Howard <phoward@gme.net.au> [trini: Add config file, update for ..._ether_addr() -> ..._ethaddr() rename] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | integrator: stop zeroing the gd flagsLinus Walleij2015-04-23-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This assignment conflicts with code that add flags with gd->flags |= FOO prior to the execution of this function. Seems like a historical artifact and creates bugs with early alloc(). Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | | ARM: integrator: move board select into mach-integrator/KconfigMasahiro Yamada2015-04-23-103/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board/SoC select menu in arch/arm/Kconfig is still cluttered. Add ARCH_INTEGRATOR into arch/arm/Kconfig and move the board select under arch/arm/mach-integrator. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Linus Walleij <linus.walleij@linaro.org>
* | | | vexpress64: use DM for all vexpress64 boardsLinus Walleij2015-04-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d8bafe1310487ba0e0785997726b4792072178d3 "ARMv8: enable DM in vexpress64 board" only enabled DM for the simulated vexpress64 board (FVP) with the hardcoded clock value for the simulated board, causing a console regression on the Juno board which was using a different clock setting. Fix this by enabling DM for all vexpress64 boards, defining the clock frequency per-board, deleting the static array of PL01x ports from the config file and relying solely on the port defined in the boardfile using platform data. Cc: David Feng <fenghua@phytium.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | board/BuR/tseries: change pinmuxHannes Petermaier2015-04-23-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | some pins on the board have been rerouted to other peripherals, so we change the pinmux to apply with hardware-design. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
* | | | board/BuR/tseries: reactivate NAND-boardHannes Petermaier2015-04-23-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND-version has been become a bit orphan. Now we need to reactivate it, so bring necessary things: - loading devicetree - switch control signal to correct pins - setup pinmux - default-environment up to date. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
* | | | board/BuR/common: simplify access to devicetreeHannes Petermaier2015-04-23-59/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead of polling everytime the environment, we take usage of the global gd->fdt_blob variable and check it only against NULL. Variable "dtbaddr" from environment is needed only one time on loading the devicetree within "load_devicetree()" Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
* | | | stm32f4: Add support for stm32f429-discovery boardrev13@wp.pl2015-04-22-0/+358
|/ / / | | | | | | | | | | | | Signed-off-by: Kamil Lulko <rev13@wp.pl> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | powerpc/t2080rdb: update ddr to support 1866MT/sShengzhou Liu2015-04-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB. Enable CONFIG_CMD_MEMTEST as well. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | board/t208xrdb: VID supportYing Zhang2015-04-20-0/+7
| |/ |/| | | | | | | | | | | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | ahci: mmio_base is a virtual addressScott Wood2015-04-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't store it in a u32. Don't dereference the bus address as if it were a virtual address (fixes 284231e49a2b4 ("ahci: Support splitting of read transactions into multiple chunks")). Fixes crash on boot in MPC8641HPCN_36BIT target. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Vadim Bendebury <vbendeb@chromium.org> Acked-by: York Sun <yorksun@freescale.com>
* | dm: sunxi: Support driver model for EthernetSimon Glass2015-04-18-3/+7
| | | | | | | | | | | | | | | | | | Adjust the Ethernet initialisation code to support driver model. It is no-longer necessary to call designware_initialize(). The device will be probed when it is used. The PHY type and GMAC base will come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Kconfig: Move CONFIG_DESIGNWARE_ETH to KconfigSimon Glass2015-04-18-6/+6
| | | | | | | | | | | | | | | | | | | | Move this to Kconfig and clean up board config files that use it. Also rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists in drivers/net/Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Version 1: Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: cosmetic: Name ethaddr variables consistentlyJoe Hershberger2015-04-18-58/+58
| | | | | | | | | | | | | | | | Use "_ethaddr" at the end of variables and drop CamelCase. Make constant values actually 'const'. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: select CONFIG_DM* optionsMasahiro Yamada2015-04-18-78/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As mentioned in the previous commit, adding default values in each Kconfig causes problems because it does not co-exist with the "depends on" syntax. (Please note this is not a bug of Kconfig.) We should not do so unless we have a special reason. Actually, for CONFIG_DM*, we have no good reason to do so. Generally, CONFIG_DM is not a user-configurable option. Once we convert a driver into Driver Model, the board only works with Driver Model, i.e. CONFIG_DM must be always enabled for that board. So, using "select DM" is more suitable rather than allowing users to modify it. Another good thing is, Kconfig warns unmet dependencies for "select" syntax, so we easily notice bugs. Actually, CONFIG_DM and other related options have been added without consistency: some into arch/*/Kconfig, some into board/*/Kconfig, and some into configs/*_defconfig. This commit prefers "select" and cleans up the following issues. [1] Never use "CONFIG_DM=n" in defconfig files It is really rare to add "CONFIG_FOO=n" to disable CONFIG options. It is more common to use "# CONFIG_FOO is not set". But here, we do not even have to do it. Less than half of OMAP3 boards have been converted to Driver Model. Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is weird. Instead, add "select DM" only to appropriate boards, which eventually eliminates "CONFIG_DM=n", etc. [2] Delete redundant CONFIGs Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again in configs/sandbox_defconfig. Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and defines it also in omap3_beagle_defconfig and devkit8000_defconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | dm: usb: Drop the EHCI weak functionsSimon Glass2015-04-18-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | These are a pain with driver model because we might have different EHCI drivers which want to implement them differently. Now that they use consistent function signatures, we can in good conscience move them to a struct. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de> Fix non-driver-model EHCI to set up the EHCI operations correctly: Signed-off-by: Tom Rini <trini@konsulko.com>
* | dm: usb: Pass EHCI controller pointer to ehci_powerup_fixup()Simon Glass2015-04-18-1/+2
| | | | | | | | | | | | | | | | Adjust this function so that it is passed an EHCI controller pointer so that implementations can look up their controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
* | exynos: cros_ec: Drop unnecessary initSimon Glass2015-04-18-12/+0
| | | | | | | | | | | | | | Since driver model will probe the EC when it is first used, we do not need to init it explicitly. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-16 17:21:05 +0000