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* kirkwood: add support for D-Link DNS-325Stefan2012-02-12-0/+453
| | | | | | | | This patch adds support for D-Link DNS-325 ShareCenter NAS. Signed-off-by: Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net> Cc: prafulla@marvell.com Cc: albert.u.boot@aribaud.net
* tt01: add MMC supportHelmut Raiger2012-02-12-2/+32
| | | | | | | | board_mmc_init() initializes the pins of SDHC1 and turns on V_MMC1 of the PMIC. Config adds support for EXT2 and FAT. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
* imx6: mx6qarm2: updated board_mmc_getcd() to the new prototypeStefano Babic2012-02-12-4/+5
| | | | | | | | | | | | Commit 314284b1567f1ce29c19060641e7f213146f7ab8 has changed board_mmc_getcd() function prototype, while mx6qarm2 has still the old one. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <jason.hui@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org>
* i.mx6q: mx6qsabrelite: Add the ethernet function supportJason Liu2012-02-12-0/+108
| | | | | | | Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org> CC: Jason Liu <jason.hui@linaro.org> CC: Stefano Babic <sbabic@denx.de>
* i.mx6q: mx6qsabrelite: Setup uart1 pinmuxTroy Kisky2012-02-12-0/+6
| | | | | | | | | | | This allows the Linux kernel to use UART1 before pinmux support is added for UART1 Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Jason Liu <jason.hui@linaro.org> CC: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* sdhc_boot: Introduce CONFIG_FSL_FIXED_MMC_LOCATION optionFabio Estevam2012-02-12-1/+1
| | | | | | | | | | | | | | | | | | | Since commit 97039ab98 (env_mmc: Allow board code to override the environment address) mmc_get_env_addr is a weak-aliased function in common/env_mmc.c The mmc_get_env_addr implementation that exists at board/freescale/common/sdhc_boot.c is meant to be used only for PowerPC boards, but currently it is being used for all platforms that have CONFIG_ENV_IS_IN_MMC defined. Introduce CONFIG_FSL_FIXED_MMC_LOCATION so that the boards that need to use the mmc_get_env_addr version from board/freescale/common/sdhc_boot.c could activate this config option on their board file. This fixes the retrieval of CONFIG_ENV_OFFSET on non-PowerPC boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefano Babic <sbabic@denx.de>
* arm, davinci: cam_enc_4xx board updatesHeiko Schocher2012-02-12-5/+665
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - CONFIG_SYS_MMC_ENV_DEV, needed if environment on mmc - wait for 1 second timer in board_late_init() only, if timer is running. - add UBI/UBIFS support - add FIT images support - menu support - U-Boot max size now 0xa0000 - SPL now Block 0 page 0 - new MTD partitioning 0x00000000 SPL 0x00020000 UBL-Header 0x00040000 UBL-Header 0x00060000 UBL-Header 0x00080000 UBoot (0xa0000(U-Boot length) + 0x60000(3 spare blocks)) 0x00180000 ENV- Variablen (1) 0x001a0000 ENV- Variablen (2) 0x001c0000 ENV- Variablen (reserved for Bad Block) 0x001e0000 ENV- Variablen (reserved for Bad Block) 0x00200000 UBI-Device UBI Volumes: „default“: contain environment-default values „rootfs1“: UBIFS root-fs (1); contain linux kernel image „rootfs2“: UBIFS root-fs (2); contain linux kernel image „data-ro“: UBIFS data (read only) „data-rw“: UBIFS data (read/write) - new environment variables: - app_reset (this is only passed per cmdline to linux) - dvn_app_vers string from ramdisk description contained in the FIT image - dvn_boot_vers string from ubootimage description contained in the FIT image - saveparms, restoreparms, restoretmpparms, savetmpparms helper for saving network parameter. - ubiargs set ubi kernel cmdlinargs for booting with a ubifs rootfs - ubi_ubi boot with reading kernel image from ubifs, and use a ubifs as rootfs Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <tom.rini@gmail.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Wolfgang Denk <wd@denx.de>
* OMAP3: Add Corscience Tricorder boardThomas Weber2012-02-12-0/+526
| | | | | | | | | Tricorder is a board which is very similar to the Devkit8000. It is designed as a base platform for further medical devices. www.corscience.de/en/medical-engineering/products/multiparameter/mp10-board.html Signed-off-by: Thomas Weber <weber@corscience.de>
* Beagleboard: Correct memory size on rev C4robertcnelson@gmail.com2012-02-12-0/+7
| | | | | | | The logic for the rev C4 boards was missing one of the cases (variant with Micron NAND and 2x128MB). Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
* tegra: Use funcmux for MMC on seaboardSimon Glass2012-02-12-17/+4
| | | | | | | Use the new funcmux_select() feature to set up the MMC pin mux. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Use funcmux for MMC on harmonySimon Glass2012-02-12-15/+4
| | | | | | | Use the new funcmux_select() feature to set up the MMC pin mux. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Use funcmux for MMC on tamontenSimon Glass2012-02-12-8/+2
| | | | | | | Use the new funcmux_select() feature to set up the MMC pin mux. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: Add support for Compal Paz00 (Toshiba AC100)Stephen Warren2012-02-12-0/+122
| | | | | | | | | | | | | | | | | | | | The Toshiba AC100 (Compal code-name Paz00, aka Dynabook AZ) is a netbook derived from the NVIDIA Tegra Harmony reference board. It ships with Android, but is often repurposed to run Linux. This patch adds just enough support to get a U-Boot serial console, and the ability access built-in eMMC and the external SD slot. v2: * Rebased on latest HEAD, incorporated changes made to other board files. * Moved board files from board/nvidia to board/compal. * Switched to correct odmdata value. This required add the previous patch to fix U-Boot's interpretation of the odmdata RAM size field. * Removed nvmem= from default Linux kernel command-line; no drivers use the reserved memory yet, so there's no point reserving it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: AM33XX: Add i2c supportPatil, Rachna2012-01-23-0/+20
| | | | | | | Add i2c driver board hookup for AM335X EVM Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Patil, Rachna <rachna@ti.com>
* overo: add SPL supportAndreas Müller2012-01-16-29/+69
| | | | | | | | | | * implementation based on ti beagleboard/omap3evm * timing data and i2c workaround for revision 0 boards taken from x-loader * run-tested with overo revision 0 and 1 / boot from NAND and SDcard * run-tested with x-loader Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
* board/overo/overo.c: replace printf with one argument by putsAndreas Müller2012-01-16-7/+7
| | | | Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
* ARM:AM33XX: Add SPL support for AM335X EVMChandan Nath2012-01-16-26/+2
| | | | | | | | | | | This patch is added to support SPL feature on AM335X platform. In this patch, MMC1 is configured as boot device for SPL and support for other devices will be added in the next patch series. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* ARM:AM33XX: Add mmc/sd supportChandan Nath2012-01-16-0/+21
| | | | | | | | | This patch add supports for mmc/sd driver on AM335X platform. PLL and pinmux configurations for mmc/sd are configured in this patch. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* cm-t35: use the new EEPROM module to read the MAC addressNikita Kiryanov2012-01-16-3/+54
| | | | | | | | | Switch to the new EEPROM module and fix the problem of MAC address being read from the wrong offset due to lack of distinction between EEPROM layouts. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* cm-t35: pass correct revision information to LinuxNikita Kiryanov2012-01-16-0/+28
| | | | | | | Read revision from EEPROM and pass it to Linux. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* cm-t35: add EEPROM module and pass Linux a serial numberNikita Kiryanov2012-01-16-1/+92
| | | | | | | | Add board specific EEPROM handling module, read the serial number from the EEPROM and pass it to Linux. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* cm-t35: various cleanupsNikita Kiryanov2012-01-16-6/+4
| | | | | | | | | Move #ifdef CONFIG_SMC911X out of board_eth_init() function, simplify the board_mmc_init() function, and enclose handle_mac_address() in the CONFIG_SMC911X. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* beagle: add eeprom expansion board info for bct brettl3Peter Meerwald2012-01-16-0/+4
| | | | | | | this is for a prototyping board vendor/product ids have been added to http://elinux.org/BeagleBoardPinMux#List_of_Vendor_and_Device_IDs
* ARMV7: Add support For Logic OMAP35x/DM37x modulesPeter Barada2012-01-16-0/+336
| | | | | | | | | | | | This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo reference boards. It assumes U-boot is loaded to SDRAM with the help of another small bootloader (x-load) running from SRAM. Signed-off-by: Peter Barada <peter.barada@logicpd.com> Cc: Tom Rini <tom.rini@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm, davinci: Change byte order of RTC kick register valuesChristian Riesch2012-01-16-2/+2
| | | | | | | | Now the values in the defines agree with those in the manuals. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de>
* i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite boardJason Liu2012-01-16-0/+363
| | | | | | | | Add the initial support for Freescale i.MX6Q Sabre Lite board Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Jason Liu <jason.hui@linaro.org> CC: Eric Nelson <eric.nelson@boundarydevices.com>
* m28evk: Remove 'all' target from MakefileFabio Estevam2012-01-16-2/+0
| | | | | | | Remove 'all' target from Makefile, as this is unused code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* mx28evk: Remove 'all' target from MakefileFabio Estevam2012-01-16-2/+0
| | | | | | | Remove 'all' target from Makefile, as this is unused code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* mx28evk: Add initial support for MX28EVK boardFabio Estevam2012-01-16-0/+370
| | | | | | | | | | | Add initial support for Freescale MX28EVK board. Tested boot via SD card and by loading a kernel via TFTP through the FEC interface. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx28: Let dram_init be common for mx28Fabio Estevam2012-01-16-17/+1
| | | | | | | | Let dram_init function be a common function, so that other mx28 boards can reuse it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* mx28: Let imx_get_mac_from_fuse be common for mx28Fabio Estevam2012-01-16-35/+0
| | | | | | | | | Let imx_get_mac_from_fuse function be a common function, so that other mx28 boards can reuse it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* net: imx: Add multi-FEC support for imx_get_mac_from_fuseFabio Estevam2012-01-16-2/+2
| | | | | | | | | | Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter. This feature is important on mx28 SoC for example that has two FEC ports. Cc: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.mx6q: mx6qarm2: Enable the usboh3 clockEric Nelson2012-01-16-1/+1
| | | | | | | | | Bits 0 and 1 of CCM_CCGR7 are the usboh3 clock enable bits. Enabling this clock is necessary for the USB download. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> CC: Jason Hui <jason.hui@linaro.org> Acked-by: Jason Hui <jason.hui@linaro.org>
* i.mx6q: arm2: Add the enet function supportJason Liu2012-01-16-0/+90
| | | | | | | | | This enable the network function on the i.mx6q armadillo2 board(arm2), thus we can use tftp to load image from network. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jason Liu <jason.hui@linaro.org> Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
* openrisc: Add openrisc-generic example boardStefan Kristiansson2012-01-13-0/+1079
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-01-13-68/+164
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init to be frequency aware sbc8548: enable support for hardware SPD errata workaround sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: Make enabling SPD RAM configuration work sbc8548: Fix LBC SDRAM initialization settings sbc8548: enable ability to boot from alternate flash sbc8548: relocate 64MB user flash to sane boundary Revert "SBC8548: fix address mask to allow 64M flash" MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM eXMeritus HWW-1U-1A: Minor environment variable tweaks
| * sbc8548: Fix up local bus init to be frequency awarePaul Gortmaker2012-01-11-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting the LCRR_EADC bit. Snooping with a hardware debugger also showed we had LCRR_DBYP set, since we were setting it based on a read of an uninitialized lcrr read via clkdiv. Borrow from the code in the tqm85xx.c support to add LBC frequency aware masking of these bits. This change will correct reliability issues associated with trying to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to Keith Savage for assistance in diagnosing the root cause of this. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: enable support for hardware SPD errata workaroundPaul Gortmaker2012-01-11-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: relocate fixed ddr init code to ddr.c filePaul Gortmaker2012-01-11-44/+48
| | | | | | | | | | | | | | | | Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: Make enabling SPD RAM configuration workPaul Gortmaker2012-01-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, SPD configuration of RAM was non functional on this board. Now that the root cause is known (an i2c address conflict), there is a simple end-user workaround - remove the old slower local bus 128MB module and then SPD detection on the main DDR2 memory module works fine. We make the enablement of the LBC SDRAM support conditional on being not SPD enabled. We can revisit this dependency as the hardware workaround becomes available. Turning off LBC SDRAM support revealed a couple implict dependencies in the tlb/law code that always expected an LBC SDRAM address. This has been tested with the default 256MB module, a 512MB a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration worked fine in all cases. The default configuration remains to go with the hard coded DDR config, so the default build will continue to work on boards where people don't bother to read the docs. But the advantage of going to the SPD config is that even the small default module gets configured for CL3 instead of CL4. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: Fix LBC SDRAM initialization settingsPaul Gortmaker2012-01-11-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were cloned from the mpc8548cds platform which has a different memory layout (1/2 the size). Set the values by comparing to the register file for the board used during JTAG init sequence: LSDMR1 0x2863B727 /* PCHALL */ LSDMR2 0x0863B727 /* NORMAL */ LSDMR3 0x1863B727 /* MRW */ LSDMR4 0x4063B727 /* RFEN */ This differs from what was there already in that the RFEN is not bundled in all four steps implicitly, but issued once as the final step. The other difference seen when comparing vs. the register file init, is that since the memory is split across /CS3 and /CS4, the dummy writes need to go to 0xf000_0000 _and_ to 0xf400_0000. We also rewrite the final LBC SDRAM inits as macros, as there is no real need for them to be a local variable that is modified on the fly at runtime. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: enable ability to boot from alternate flashPaul Gortmaker2012-01-11-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has an 8MB soldered on flash, and a 64MB SODIMM flash module. Normally the board boots from the 8MB flash, but the hardware can be configured for booting from the 64MB flash as well by swapping CS0 and CS6. This can be handy for recovery purposes, or for supporting u-boot and VxBoot at the same time. To support this in u-boot, we need to have different BR0/OR0 and BR6/OR6 settings in place for when the board is configured in this way, and a different TEXT_BASE needs to be used due to the larger sector size of the 64MB flash module. We introduce the suffix _8M and _64M for the BR0/BR6 and the OR0/OR6 values so it is clear which is being used to map what specific device. The larger sector size (512k) of the alternate flash needs a larger malloc pool, otherwise you'll get failures when running saveenv, so bump it up accordingly. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: relocate 64MB user flash to sane boundaryPaul Gortmaker2012-01-11-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current situation has the 64MB user flash at an awkward alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole for the soldered on boot flash @ EOM. But to switch to optionally supporting booting off the 64MB flash, the 64MB will then be mapped at the sane address of 0xfc00_0000. This leads to awkward things when programming the 64MB flash prior to transitioning to it -- i.e. even though the chip spans from 0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was in the right place when JP12/SW2.8 were switched to make the 64MB on /CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff) We also have to have three TLB entries responsible for dealing with mapping the 64MB flash due to this 8MB of misalignment. In the end, there is address space from 0xec00_0000 to 0xefff_ffff where we can map it, and then the transition from booting from one config to the other will be a simple 0xec --> 0xfc mapping. Plus we can toss out a TLB entry. Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot flash; this means we won't have to change it when the alternate config uses the full 64MB for booting, in TLB0. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBCPaul Gortmaker2012-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These boards were meaning to deploy this value: #define LCRR_DBYP 0x80000000 but were missing a zero, and hence toggling a bit that lands in an area marked as reserved in the 8548 reference manual. According to the documentation, LCRR_DBYP should be used as: PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock. When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle. It is recommended that PLL bypass mode be used at frequencies of 83 MHz or less. So the impact would most likely be undefined behaviour for LBC peripherals on boards that were running below 83MHz LBC. Looking at the actual u-boot code, the missing DBYP bit was meant to be deployed as follows: Between 66 and 133, the DLL is enabled with an override workaround. In the future, we'll convert all boards to use the symbolic DBYP constant to avoid these "count the zeros" problems, but for now, just fix the impacted boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2012-01-13-909/+251
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ppc4xx: board/mpl/pati: use the CFI driver for the PATI board board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board board/mpl/pip405: use the CFI driver for the PIP405 board board/mpl/common: remove the old legacy flash ppc4xx: Setup HICB on Io64
| * | board/mpl/pati: use the CFI driver for the PATI boardDavid Müller2012-01-09-2/+2
| | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| * | board/mpl/mip405: use the CFI driver for the MIP405/MIP405T boardDavid Müller2012-01-09-3/+25
| | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| * | board/mpl/pip405: use the CFI driver for the PIP405 boardDavid Müller2012-01-09-8/+26
| | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| * | board/mpl/common: remove the old legacy flashDavid Müller2012-01-09-896/+182
| | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Setup HICB on Io64Dirk Eibach2012-01-09-0/+16
| |/ | | | | | | | | | | | | The FPGA High-Speed Interconnect Bus (HICB) is now setup by u-boot. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-09 14:59:57 +0000