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* MAINTAINERS/mailmap: Update my email addressFabio Estevam2016-01-11-11/+11
| | | | | | Update my email address to the NXP account. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-01-10-6/+7
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| * cgtqmx6eval: README: Fix parameter of 'sf write' commandOtavio Salvador2016-01-10-1/+5
| | | | | | | | | | | | | | | | | | | | | | 'sf command' should receive the length in sector boundaries, so fix it accordingly. Also, show the steps to set the server and board IP addresses for making the steps clearer. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6cuboxi: Remove obsolete commentFabio Estevam2016-01-10-4/+0
| | | | | | | | | | | | | | | | | | We currently support various versions of Solidrun mx6 boards, so remove the obsolete comment. Reported-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * mx6cuboxi: Fix the reset delay for the AR8035 PHYFabio Estevam2016-01-10-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional: Booting from net ... FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. As per the AR8035 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and keep the reset low for 10ms. Also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros PHY can be loaded as per Troy Kisky's suggestion. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-01-08-69/+6
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| * pfuze: Fix unsigned variable for less-than-zero comparisonYe.Li2016-01-07-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | According to the Coverity result, a unsigned int variable is used fo less- than-zero comparison, the result is never true. Need to fix the variable type to signed int. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * wandboard: Simplify the Ethernet PHY configurationFabio Estevam2016-01-07-34/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the AR8031 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros 8031 PHY driver can be loaded automatically. This results in a simpler code. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * mx6sabresd: Simplify the Ethernet PHY configurationFabio Estevam2016-01-07-34/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the AR8031 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros 8031 PHY driver can be loaded automatically. This results in a simpler code. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | MAINTAINERS, .mailmap: Update my email addressYork Sun2016-01-08-2/+2
|/ | | | | | Change from yorksun@freescale.com to york.sun@nxp.com. Signed-off-by: York Sun <york.sun@nxp.com>
* qemu-ppce500: pass 'range_id' around in pci_map_regionMiao Yan2016-01-04-1/+1
| | | | | | | | | | In pci_map_region(), pass 'range_id' to fdt_read_range(), otherwise the same address will be mapped again in other calls to pci_map_region() Signed-off-by: Miao Yan <yammiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-01-03-8/+93
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| * imx: mx6qsabreauto: support lvds displayPeng Fan2016-01-03-3/+84
| | | | | | | | | | | | | | | | | | | | | | Move setup_display from board_early_init_f to board_init. Add more clock settings. Add blacklight iomux setting. Add display_info_t info for the lvds screen. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * cgtqmx6eval: fix pad configuration for SPI busMichael Schanz2016-01-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the macro SETUP_IOMUX_PAD(...) rather than imx_iomux_v3_setup_multiple_pads(...) in order to setup the pin configuration for ECSPI1. ARRAY_SIZE(pads) provides the wrong size for imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)) in case of MX6QDL. In the particular case, the content of GPR12 is overwritten and the IPG/AHB/ATB/ATP clocks are deactivated. Therefore, the connection to the system via JTAG is not possible anymore. Furthermore, kernel version 3.0.35 hangs during bootprocess in the function etm_init(). Signed-off-by: Michael Schanz <michael.schanz@congatec.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * mx6sxsabresd: Fix Ethernet PHY reset sequenceFabio Estevam2015-12-07-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional. This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. Fix this by calling enable_fec_anatop_clock() earlier and also by adding a 10ms reset delay as recommended in the AR8031 datasheet. Suggested-by: Jörg Krause <joerg.krause@embedded.rocks> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * cgtqmx6eval: Fix defconfig nameOtavio Salvador2015-12-07-1/+1
| | | | | | | | | | | | After the conversion to SPL the defconfig was renamed, so adjust it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-12-24-39/+36
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: include/configs/axs101.h Signed-off-by: Tom Rini <trini@konsulko.com>
| * | arm: socfpga: Fix i2c mux on cyclone5-socdk boardChin Liang See2015-12-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated pinmux group GENERALIO[15-16] for i2c. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: shengjiangwu <shengjiangwu@icloud.com>
| * | arm: socfpga: Fix USB doesn't work on socdk boardshengjiangwu2015-12-23-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated pinmux group EMACIO[1-8] and EMACIO[10-13] for USB. Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
| * | arm: socfpga: Fix QSPI doesn't work on socdk boardshengjiangwu2015-12-22-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
| * | arm: socfpga: Fix emac1 doesn't work on socdk boardshengjiangwu2015-12-22-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
| * | net: designware: Zap CONFIG_DW_AUTONEGMarek Vasut2015-12-22-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This symbol is not used anywhere, so remove it. For spear600, remove it from the board file, since the symbol is not defined for spear600 either. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | | sun5i: Add defconfig and dts file for the Empire Electronix D709 tabletHans de Goede2015-12-21-0/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Empire Electronix D709 tablet is a fairly standard 7" A13 tablet, featuring usb-wifi, a micro-sd slot, micro-usb otg and headphone jack. Empire Electronix is written on the back of the tablet, the D709 model info can be found in the about tablet menu in android. The PCB has no markings to speak of. This dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | arm: socfpga: Drop the board boilerplateMarek Vasut2015-12-20-313/+0
| | | | | | | | | | | | | | | | Drop all the common board code, since it is not completely useless. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: socrates: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
* | arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
* | arm: socfpga: mcvevk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
* | arm: socfpga: cyclone5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
* | arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
* | arm: socfpga: socrates: Remove Micrel PHY configurationMarek Vasut2015-12-20-40/+0
| | | | | | | | | | | | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: sockit: Remove Micrel PHY configurationMarek Vasut2015-12-20-40/+0
| | | | | | | | | | | | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: de0_nano: Remove Micrel PHY configurationMarek Vasut2015-12-20-50/+0
| | | | | | | | | | | | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: cyclone5-socdk: Remove Micrel PHY configurationMarek Vasut2015-12-20-40/+0
| | | | | | | | | | | | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | arm: socfpga: arria5-socdk: Remove Micrel PHY configurationMarek Vasut2015-12-20-40/+0
| | | | | | | | | | | | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-12-18-42/+12048
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| * | microblaze: Do not handle watchdog and gpio in SPLMichal Simek2015-12-18-1/+2
| | | | | | | | | | | | | | | | | | watchdog and gpio are not validated for SPL that's why do not use them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Remove support for LL_TEMACMichal Simek2015-12-18-41/+0
| | | | | | | | | | | | | | | | | | | | | LL_TEMAC is available at big endian MB and it is not properly tested that's why the patch removes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Add default ps7_init_gpl.c/h for ZYBONathan Rossi2015-12-18-0/+12046
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init is generated by the Vivado 2015.3 tools using the system configuration provided by Digilent located on their website. Update the kconfig so that the defconfig is not overrided to use the custom init ps7_init_gpl target by default. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2015-12-17-35/+35
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| * | usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.hMarek Vasut2015-12-17-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the global s3c_udc.h header to dwc2_udc.h. The rename is done automatically: $ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \ `git grep "s3c_udc\.h" | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
| * | usb: s3c-otg: Rename s3c_udc_probe() functionMarek Vasut2015-12-17-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the second and final to rename global symbol, the s3c_udc_probe() function. The rename is done automatically: $ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \ `git grep s3c_udc_probe | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
| * | usb: s3c-otg: Rename struct s3c_plat_otg_dataMarek Vasut2015-12-17-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the first to rename global symbol, the struct s3c_plat_otg_data. The rename is done automatically: $ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \ `git grep s3c_plat_otg_data | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-17-8/+8
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| * | | armv8/ls1043aqds/rcw: change core frequency to 1600MHzMingkai Hu2015-12-17-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change RCW for SD boot and NAND boot. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls1043ardb/rcw: change core frequency to 1600MHzMingkai Hu2015-12-17-4/+4
| |/ / | | | | | | | | | | | | | | | | | | Change RCW for SD boot and NAND boot. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-12-16-0/+71
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| * | rockchip: Add basic support for kylin boardhuang lin2015-12-13-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | kylin board use rk3036 SOC, 512M sdram, 8G emmc. This add some basic files required to allow the board to output serial message and can run command(mmc info etc). Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-14-160/+161
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| * | | armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-13/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8: fsl-layerscale: Rewrite reserving memory for MC and debug serverYork Sun2015-12-15-51/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-10 01:45:19 +0000