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* ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.hLokesh Vutla2013-06-10-5/+5
| | | | | | | To be consistent with other ARM platforms, renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-06-10-18/+30
| | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* am33xx: Board: Make CPSW section of ethernet initialization depend on CPSW ↵Joel A Fernandes2013-06-10-0/+2
| | | | | | | | driver Not doing so breaks cases where CPSW is not required such as for USB RNDIS network boot. Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-08-4/+951
|\ | | | | | | | | Conflicts: drivers/serial/Makefile
| * vf610twr: Drop unneeded 'status' variableFabio Estevam2013-06-06-4/+1
| | | | | | | | | | | | | | No need to use the 'status' variable, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
| * Add support for Congatec Conga-QEVAl boardSARTRE Leo2013-06-04-0/+238
| | | | | | | | | | | | | | | | | | | | Add minimal support (only boot from mmc device) for the Congatec Conga-QEVAl Evaluation Carrier Board with conga-Qmx6q (i.MX6 Quad processor) module. Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * wandboard: Enable HDMI splashscreenFabio Estevam2013-06-03-0/+98
| | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: mx6qsabrelite/nitrogen6x: Remove incorrect setting of gpio CS signalAndrew Gabbasov2013-06-03-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro (shifted and or'ed with chip select), so it's incorrect to pass that macro directly as an argument to gpio_direction_output() call. Also, SPI driver sets the direction and initial value of a gpio, used as a chip select signal, before any actual activity happens on the bus. So, it is safe to just remove the gpio_direction_output call, that works incorrectly, thus making no effect, anyway. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Tested-by: Robert Winkler <robert.winkler@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * mx6qsabreauto: Add Port Expander resetRenato Frias2013-06-03-0/+7
| | | | | | | | | | | | | | | | There are 3 IO expanders on the mx6qsabreauto all reset by the same GPIO, just set it to high to use the IO. Signed-off-by: Renato Frias <b13784@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * mx6qsabreauto: Add i2c to mx6qsabreauto boardRenato Frias2013-06-03-0/+50
| | | | | | | | | | | | | | | | | | | | Add i2c2 and 3 to mx6qsabreauto board, i2c3 is multiplexed use gpio to set steering. Signed-off-by: Renato Frias <b13784@freescale.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * arm: vf610: Add basic support for Vybrid VF610TWR boardAlison Wang2013-06-03-0/+482
| | | | | | | | | | | | | | | | | | | | | | VF610TWR is a board based on Vybrid VF610 SoC. This patch adds basic support for Vybrid VF610TWR board. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * wandboard: fix typo in READMELuka Perkov2013-05-16-2/+2
| | | | | | | | | | | | Fix typo in wandboard README file. Signed-off-by: Luka Perkov <luka@openwrt.org>
| * mx23evk: Add splash screen supportFabio Estevam2013-05-16-0/+38
| | | | | | | | | | | | Enable display support. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx28evk: Add splash screen supportFabio Estevam2013-05-16-0/+39
| | | | | | | | | | | | Enable display support. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.cTom Rini2013-06-05-0/+36
| | | | | | | | | | | | | | | | | | | | | | We need to call the save_omap_boot_params function on am33xx/ti81xx and other newer TI SoCs, so move the function to boot-common. Only OMAP4+ has the omap_hw_init_context function so add ifdefs to not call it on am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx boards. Reviewed-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | tx25: copy SPL directly, not using relocate_code.Albert ARIBAUD2013-05-30-1/+15
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | mx31pdk: copy SPL directly, not using relocate_code.Albert ARIBAUD2013-05-30-1/+15
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-1980/+1255
|\ \ | | | | | | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * | powerpc/b4860qds: Add LAW Target ID and Create LAW entry for MapleShaveta Leekha2013-05-24-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: fix mdio mux for 10G portShaohui Xie2013-05-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in eth port enum structure, it will assign mdio mux depend on this assumption. This is not true with Fman V3, which added more 1G ports after port DTSEC5 in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux. So we use dynamic index for 10G ports instead of hardcoded enum value when doing mdio mux for 10G ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p2041: fix serdes reference clock frequency display for PC boardShaohui Xie2013-05-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PC board has different serdes clock setting with PB board, it uses same serdes frequency setting on bank2 as on bank1. PC board can be distingushed from PB board by checking CPLD version, if running on PC board, then fix the serdes reference clock frequency of bank2. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4860: fix for Serdes connectivity to SFP'sShaveta Leekha2013-05-24-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Crossbar switches were wrongly programmed to route the CPRI lanes to SFP as the connectivity table was not correct. Modified it correctly for SFPs connections. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: fix PHY reset timeout issueShengzhou Liu2013-05-24-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card has different PHY address against previous SGMII card. We check the type of card in slots and set correct PHY address to avoid complainning "PHY reset timed out" during u-boot booting up. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4qds: Add SW7[4] in the DIP switch displayYork Sun2013-05-24-2/+3
| | | | | | | | | | | | | | | | | | | | | SW7[4] is the new bit which controls the mapping of eMMC vs SDHC. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32MStephen George2013-05-24-4/+6
| | | | | | | | | | | | | | | | | | | | | Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: enable PBL tool supportShaohui Xie2013-05-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4qds: use clock measurement for sysclk and ddr clockEd Swarthout2013-05-24-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QIXIS measurement registers to obtain sysclk and ddr clock. This allows using non-standard clock speeds, set by directly writing to clock chip or store the values in qixis clock data eeprom. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/qixis: add clock measurement registersEd Swarthout2013-05-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QIXIS includes frequency measurement functions for each major processor clock input. After reset (and after clocks are stable), QIXIS measures the clocks against a reference frequency and stores the results in CLK_FREQ registers. A base register supplies a multiplier which allows directly obtaining the measured value, without requiring knowledge of the target system or QIXIS core frequency. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | T4240/ramboot: enable PBL tool for T4240Shaohui Xie2013-05-24-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: Add VDD overrideYork Sun2013-05-24-2/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: Add board detail for bdinfo commandYork Sun2013-05-24-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print more detail information including core voltage, RCW source, switch settings, etc. with bdinfo command. Signed-off-by: York Sun <yorksun@freescale.com> CC: Wolfgang Denk <wd@denx.de> CC: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-97/+626
| |\ \
| | * | T4240/eth: fix SGMII card PHY addressShaohui Xie2013-05-14-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card assumed to be used by default, but if SGMII card is used, it will use different PHY address, but we don't know which card is used until we access PHY on the card. So we check the card type slot by slot, if we can read a PHY ID by reading a SGMII PHY address on a slot, then the slot must have a SGMII card pluged, we mark all ports on that slot, and fix dts to use the SGMII card PHY address when doing dts fixup for the marked ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4qds: Fix disabling remote I2C connectionEd Swarthout2013-05-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/b4860qds: Assign DDR address in board fileYork Sun2013-05-14-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | T4240/net: use QSGMII card PHY address by defaultShaohui Xie2013-05-14-56/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-14-14/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: Add voltage ID supportYork Sun2013-05-14-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: Update DDR timing tableYork Sun2013-05-14-22/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | T4/serdes: fix the serdes clock frequencyRoy Zang2013-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-1736/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
| * | | blackfin: bf609: add softswitch config commandBob Liu2013-05-13-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add softswitch_output command for bf609-ezkit to enable softswitches. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | | blackfin: bf609: implement soft switchSonic Zhang2013-05-13-0/+251
| |/ / | | | | | | | | | | | | | | | | | | | | | Set up soft switch pins properly in board init code. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Scott Jiang <scott.jiang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
| * | openrisc: move board linker script(s) to a common in cpu/Stefan Kristiansson2013-05-10-77/+0
| | | | | | | | | | | | | | | | | | Unifies the openrisc boards linker scripts into a common one. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
| * | openrisc: specify a memory region for u_boot_listsStefan Kristiansson2013-05-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Since there are two memory areas defined, vectors and ram, the linker will error when neither of them are specified for a section. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
| * | Fix references to the documentation filesAnatolij Gustschin2013-05-10-42/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boot image configuration files refer to the appropriate documentation file, but these references contain typos in the directory and file name. Fix them. Also fix reference to doc/README.SPL file. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | gpio: Add support for microblaze xilinx GPIOMichal Simek2013-05-09-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microblaze uses gpio which is connected to the system reset. Currently gpio subsystem wasn't used for it. Add gpio driver and change Microblaze reset logic to be done via gpio subsystem. There are various configurations which Microblaze can have that's why gpio_alloc/gpio_alloc_dual(for dual channel) function has been introduced and gpio can be allocated dynamically. Adding several gpios IP is also possible and supported. For listing gpio configuration please use "gpio status" command This patch also remove one compilation warning: microblaze-generic.c: In function 'do_reset': microblaze-generic.c:38:47: warning: operation on '*1073741824u' may be undefined [-Wsequence-point] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Tegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhuTom Warren2013-05-28-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both board and board_name == beaver. Didn't test as I have no T30 Beaver board here. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | | ARM: Add Seagate GoFlex Home supportSuriyan Ramasami2013-05-23-0/+408
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Seagate GoFlex Home support Start with dockstar configuration define support for RTC, DATE, SATA and EXT4FS Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
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