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* MLK-12735 mx6qpsabresd: Update DDR script to version 1.14Ye Li2016-04-29-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)
* MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2Anson Huang2016-04-29-59/+59
| | | | | | | | i.MX7D TO1.2 uses same DDR script as TO1.0, TO1.1 uses dedicated DDR script. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 527d57e02b05eb0166dcaa1929e46dd2357a8720)
* MLK-12694 mx6ullarm2: Remove the CD detection of SD2Ye Li2016-04-22-3/+1
| | | | | | | | | | Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause SD2 access problem even the card is inserted. Hard code the CD result to 1 to assume the card is always on. The SD driver will return other errors if the card does not exist. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 47efe2fda62297ab1da8594828cd7bd928ecbda7)
* MLK-12687 mx6ullarm2: Clean up macro usage for pins conflict devicesYe Li2016-04-21-8/+8
| | | | | | | | | | | | | | | 1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which conflicts with QSPIA and NAND, that we have to disable them at same time. 2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which conflicts with SD2 and NAND, that we have to disable them at same time. 3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK 4. Enable QSPI support for default SD boot case. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)
* MLK-12690 imx: mx6ull: fix build error for pluginPeng Fan2016-04-21-1/+1
| | | | | | | | | Fix build error for Plugin "Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor" Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 95860f1213c038ef2e5900d1874ff5398ac0be2a)
* MLK-12677 mx6ullarm2: Update DDR script to version 2.1Ye Li2016-04-20-5/+6
| | | | | | | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc Changes: Change ZQ_OFFSET to the default value:00 setmem /32 0x021B0890 = 0x00400000 Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11 setmem /32 0x020E0288 = 0x000C0030 Change duty cycle fine tune cell for SDCLK and SDQS setmem /32 0x021B08C0 = 0x00944009 Test: One mx6ull ARM2 board passed memtest. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8128b2f3b419a1d15a0489a91e56a4ac82eaf0c4)
* MLK-12616-11 imx: mx6ull: add mx6ull arm2 board supportPeng Fan2016-04-13-0/+1120
| | | | | | | | | | | | | Support mx6ull ddr3 arm2 board. DDR script version 1.1. Passed memtester on 3 boards. Take mx6ul 14x14 ddr3 arm2 as reference. Note: LCD/NAND/ECSPI not tested, need hardware rework. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 584050b98cf070bb608b652e89659ff20c47efba)
* MLK-12563: imx: mx6ul evk: fix LCD_nPWREN settingPeng Fan2016-03-25-1/+1
| | | | | | | Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3. If LCD_nPWREN is high, output is 2.4V which is not correct. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12551: imx6ul evk: fix 74LV OE usagePeng Fan2016-03-25-7/+1
| | | | | | | | | | | Fix 74LV OE gpio index. pinmux is correct, but gpio index is wrong, so gpio output will not have effect, since we use wrong GPIO5_IO18, but not correct GPIO5_IO8. And at the end of the initialization of 74lv init, should keep OE voltage level at LOW, but not high. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12483-5 mx6ul: Enable module fuse check EVK board and DDR3 ARM2 boardYe Li2016-03-25-1/+58
| | | | | | | Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for module fuse check. And modify board level codes for SD, FEC and EIM. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12442: imx: mx6qarm2: lpddr2 set dram 2 channel fixed modeAdrian Alonso2016-03-25-2/+12
| | | | | | | | | | | | | Setup MMDC in two channel fixed mode Initialize dram banks for two channel fixed mode DRAM bank = 0x00000000 -> start = 0x10000000 -> size = 0x20000000 DRAM bank = 0x00000001 -> start = 0x80000000 -> size = 0x20000000 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12371-2: imx: mx7dsabresd: fix POR reset failed after DDR enter retentionRobin Gong2016-03-25-0/+9
| | | | | | | Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR retention mode before uboot boot, so add this in DCD and plugin code. Signed-off-by: Robin Gong <yibin.gong@nxp.com> (cherry picked from commit 62248ef80dabbd7601ff4e2969368d7bf54896d9)
* MLK-12555-3 mx7dsabresd: Remove the SRS setting for wdogYe Li2016-03-25-6/+0
| | | | | | | Since the WDOG driver has updated to clear SRS at software assertion of WDOG. We don't need this in board level. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12555-2 mx6ulevk: Enable the Watchdog WDOG_B signal outputYe Li2016-03-25-0/+2
| | | | | | | | When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12555 mx6sxsabreauto: Enable the Watchdog WDOG_B signal outputYe Li2016-03-25-0/+3
| | | | | | | | When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12553 mx6sabresd: Add RGMII supportYe Li2016-03-25-0/+33
| | | | | | | Need to configure the phy AR8031 to output 125Mhz clock for ENET reference clock. And introduce a TX clock delay. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull upYe.Li2016-03-25-6/+31
| | | | | | | | | | Set the ID pin pad to pull up not the pull down at default, otherwise we can't enter the device mode, but always detect as host. After this change we have to use portA cable to play as host, and use portB cable for device. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-12531 mx6sxsabresd: Add CM4 fast boot up demoYe Li2016-03-25-0/+19
| | | | | | | | | | | | | | | | | This is a demo that CM4 will boot up by u-boot without typing any command. It boots up at u-boot early init, try to minimize the time from power up to the CM4 running. Since CM4 runs on QSPI NOR XIP, we have to disable the QSPI driver in u-boot to avoid conflict. RDC for shared GPIO1 is added, but not enabled, because the kernel is not ready for shared GPIO1. Users can uncomment the CONFIG_IMX_RDC to enable it. Some legacy codes in mx6sxsabreauto are removed. We only need this work on mx6sxsabresd as a demo. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12527-3 android: Add board support to enable android fastbootYe Li2016-03-25-1/+746
| | | | | | | | | | | Add board level support for android fastboot feature. Each board has a android specified header file for defining android related configuraitons. And add build targets for their android uboot images building. For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android fastboot exclusive with DFU. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12527-2 android: Add FSL android fastboot supportYe Li2016-03-25-0/+81
| | | | | | | | | | | | | | | | | | | | | Integrate the FSL android fastboot features into community's fastboot. 1. Use USB gadget g_dnl driver 2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and EFI partitions are not support by i.MX. 3. Add FDT support to community's android image. 4. Add a new boot command "boota" for android image boot. The boota implements to load ramdisk and fdt to their loading addresses specified in boot.img header, while bootm won't do it for android image. 5. Support the authentication of boot.img at the "load_addr" for both SD and NAND. 6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot with relevant header file "fsl_fastboot.h". While disabling the configuration, the community fastboot is used. 7. Overwrite the cmdline in boot.img by using bootargs saved in local environment. 8. Add recovery and reboot-bootloader support. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12529 mx7dsabresd: Fix soc revision check issueYe Li2016-03-25-1/+1
| | | | | | | The is_soc_rev returns true when the revision is matched, this is opposited with uboot v2015 which returns 0. Have to fix this for mx7dsabresd Signed-off-by: Ye Li <ye.li@nxp.com>
* MA-7455-1 Pico: modify Pico configuration for Brillo.Peng Fan2016-03-25-68/+24
| | | | | | | | | Modify the picosom to be suit for Brillo configurations. Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com> (cherry picked from commit 864fd4f019674e8333b1fdb91e9242ae75f35992) To align with 2016.03, fix several places. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MA-7455 Import picosom boot codesHaoran Wang2016-03-25-0/+931
| | | | | | | | | Imported the picosom boot codes and board configs from technexion. Signed-off-by: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com> (cherry picked from commit d102c193f3f903055239f07ddbaab63715dbf82f)
* MLK-12500-2 HAB: Add commented secure boot configurationsYe Li2016-03-25-0/+11
| | | | | | | | | | CONFIG_SECURE_BOOT is used for signed image building, this configuration is not enabled at default. Comment it in board header files. Users can uncomment it to enable. Also add CONFIG_CSF_SIZE for defining the CSF reserved size Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12497-2 mx7d: Add reference DDR script for mx7d TO1.0Ye Li2016-03-25-0/+691
| | | | | | | | | | | | | | | | | | | On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated. When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards), DDR data corruption occured, not able to decrease CKE delay, so we have to add extra delay on all other signals to balance it. DDR script needs to be fine-tuned according to this hardware change. For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from 533Mhz to 400Mhz. We uses TO1.1 script at default, and retains the TO1.0 script for reference. Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12497-1 mx7d: Add support for all mx7d arm2 boardsYe Li2016-03-25-0/+4422
| | | | | | | Porting all mx7d arm2 boards (mx7d 12x12 lpddr3, 12x12 ddr3, 19x19 ddr3, 19x19 lpddr2, 19x19 lpddr3) support from u-boot v2015.04. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12495 mx6: Add LDO bypass supportYe Li2016-03-25-0/+329
| | | | | | | | | | | | | | | Port LDO bypass support from v2015 to support the features: 1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12493-2 mx6ulevk: Use CONFIG_TARGET_MX6UL_9X9_EVK for 9x9 LPDDR2 scriptYe Li2016-03-25-1/+1
| | | | | | Change to use CONFIG_TARGET_MX6UL_9X9_EVK for selecting DDR script. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12493-1 Add support for various boot deviceYe Li2016-03-25-0/+4
| | | | | | | | | Add support for various boot devices like NAND, QSPINOR, SPINOR, eMMC, EIMNOR, SATA. Modify board level files to support the feature and add corresponding defconfig files Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12486-2 imx6: Add i.mx6sx/ul arm2 boardsPeng Fan2016-03-25-0/+5184
| | | | | | | | | Add i.MX6SX/UL arm2 boards support. Most code are from imx_v2015.04, but adapted to 2016.03 release. Tested on mx6ul_14x14_ddr3_arm2 and mx6sx_19x19_ddr3_arm2. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12486-1: switch to use setup_gpmi_io_clk for i.MX6ULPeng Fan2016-03-25-28/+2
| | | | | | | Add i.MX6UL support in setup_gpmi_io_clk and change mx6ul_14x14_evk to use it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12452-4 mx6sxsabreauto: Add secondary enet supportYe Li2016-03-25-7/+32
| | | | | | Add configurations and board codes for second enet. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12452-3 mx6sxsabresd: Add secondary enet supportYe Li2016-03-25-6/+31
| | | | | | Add configurations and board codes for second enet. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12452-2 mx7dsabresd: Add secondary enet supportYe Li2016-03-25-58/+54
| | | | | | Add configurations and board codes for second enet. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-17: imx: mx6sxauto: update board and headerPeng Fan2016-03-25-18/+80
| | | | | | | | | Align with imx_v2015.04 Update pmic settings. Update imximage.cfg. Enable bmode. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-16: imx: mx6sxsdb: update board and headerPeng Fan2016-03-25-17/+117
| | | | | | | | | | | | Align with imx_v2015.04. Add emmc support which needs board rework. Add I2C2. Update pmic settings. Add bmode. Move partial code from board_early_init_f to board_init. Disable PCI. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-15: imx: mx7dsdb: add RevB supportPeng Fan2016-03-25-34/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add RevB board support and Align with imx_v2015.04. imx_v2015.04 commit: " commit f026a65375094cc2c0e25ed11772aee9362ee63d Author: Ye.Li <B37916@freescale.com> Date: Thu Dec 17 11:39:09 2015 +0800 MLK-12034 imx: mx7dsabresd: Add RevB board support Since i.MX7D SDB revB board has some HW changes, we have modify the BSP file to support new pinmux. 1. OTG2 PWR pin is changed to GPIO1_IO07. 2. A enet2_en pin is added for isolating enet2 signals with EPDC, we also add support for enet2. 3. pin6 of 74LV output is changed for CSI PWDN. Set output to high to power down it. This patch also tries to get the board id and apply changes according with it. Since current RevB board does not burn GP1 fuse for board id, we have to check the TO rev instead even it is not very exact. Will update this if any new way implemented. " Also update pmic settings to align with datasheet. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-12436-14: imx: mx7dsdb: update ddr scriptPeng Fan2016-03-25-5/+22
| | | | | | | | | | | | | | | | | On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated. When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards), DDR data corruption occured, not able to decrease CKE delay, so we have to add extra delay on all other signals to balance it. DDR script needs to be fine-tuned according to this hardware change. For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from 533Mhz to 400Mhz. Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-13: mx6ulevk: update board codePeng Fan2016-03-25-7/+65
| | | | | | | | | Align with imx_v2015.04. Add nand related settings. Update qspi pad electric settings. Add usb ethernet support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-12: mx6slevk: update board codePeng Fan2016-03-25-4/+92
| | | | | | | | | | | | | | Add elan code, to handle epdc which has i2c devices. To imx_v2015.04, the two pathces are for elan. b6ba68516b681a38025252bd0ef6a6ed3e8adfa0 MLK-10215 Add elan init in i.MX6SL-EVK board 0c600f6a67f00fe0c674c08c355bea3789109679 MLK-10885 imx: mx6slevk ignore elan init when no epdc on board Align ddr script and header file to imx_v2015.04. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-10: mx6sabresd: update board code and header fileYe Li2016-03-25-19/+81
| | | | | | | | | Align board code and header file with imx_v2015.04. Update pmic settings. wrap spi code together using CONFIG_MXC_SPI macro. To i.MX6SOLO, need to define CONFIG_MX6DL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-9: mx6sabresd: update ddr scriptPeng Fan2016-03-25-82/+350
| | | | | | | | | | | | Align ddr script with imx_v2015.04 latest ddr script. mx6qp.cfg is 1.13 version http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI arik_r2_sdb_ddr3_528_1.13.inc is for sabresd Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-8: imx: mx6qsabreauto: misc board updatePeng Fan2016-03-25-35/+196
| | | | | | | | | | | | | | To Align with imx_v2015.04. 1. Add USDHC1 support on mother board 2. Add SPINOR flash support. 3. Add enet ref clk pinmux setting and enet settings 4. Use CONFIG_SYS_USE_EIMNOR to wrap eimnor settings. 5. update mmc board settings 6. update board_init and move nand settings to board_init, but not in board_early_init_f 7. update pmic settings to align with datasheet. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-7: imx: mx6qsabreauto: add solo board supportPeng Fan2016-03-25-0/+125
| | | | | | Add solo version ddr script and build target. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-6: imx: mx6dqpsabreauto: update ddr script to 1.13Peng Fan2016-03-25-5/+15
| | | | | | | | | | | | | | | | | | DDR script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI Patch in imx_v2015.04: " commit 5fb08a4dcc7b8478fc4236b90ad8dc2190cf94e7 Author: Peng Fan <Peng.Fan@freescale.com> Date: Wed Nov 4 16:30:47 2015 +0800 "MLK-11825 imx: mx6dqp: update ddr script to 1.13" " Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-5: imx: mx6qsabreauto: update ddr script filePeng Fan2016-03-25-4/+36
| | | | | | Align script file with imx_v2015.04. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12436-3: mx6qarm2: add new board revision supportPeng Fan2016-03-25-0/+294
| | | | | | | | | | | | | | Add mx6qarm2 new board revision support using mx6q pop SoC Enable DRAM support for imx6q PoP SoC with populated LPDDR2 MT42L128M64D2 DDR calibration script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69 Test result: Stress test passed. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12436-2: mx6qarm2: update ddr scriptsPeng Fan2016-03-25-1/+179
| | | | | | | | | | | | | | | | | | | | | | | ALign with imx_v2015.04. Also to lpddr2 support: From commit: "620cf5f3d4cf37b065b5857a8ea91d61bf6c471d" " Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board, but there is a problem in switching pre_periph_clk_sel to pll2_pfd2. We cannot directly change the parent of pre_periph_clk_sel as this mux is not a glitchless mux. We need to follow the correct procedure and wait for the busy bits to clear before switching. Change to follow the procedure: 1. Set periph_clk2 to OSC. 2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk , ahb_podf and axi_podf busy bits. 3. Setting the pre_periph_clk to PLL2 PFD 396M. 4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits. " Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-12436-1: mx6qarm2: support lpddr2 boardPeng Fan2016-03-25-2/+7
| | | | | | Support lpddr2 board. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12440-10 mx6dq/dl: Add plugin boot support for arm2 boardsYe Li2016-03-25-3/+1195
| | | | | | | Add plugin.S for plugin boot initialization on mx6dq/dl arm2 board. Need to enable "CONFIG_USE_PLUGIN" for this feature. Signed-off-by: Ye Li <ye.li@nxp.com>
generated by cgit v1.1 at 2024-12-18 21:50:42 +0000