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| * sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)Chen-Yu Tsai2016-10-30-1/+1
| | | | | | | | | | | | | | | | In Allwinner's SDK the A80 is clocked to 1008 MHz by default. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: add MMC pinmux setup for SDC2 on sun9iPhilipp Tomsich2016-10-30-0/+7
| | | | | | | | | | | | | | | | The A80 can support 8-bit eMMC with reset on the PC pingroups. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: enable SPL for sun9iPhilipp Tomsich2016-10-30-0/+1
| | | | | | | | | | | | | | | | | | | | Now that DRAM initialization and clock setup is supported, we can enable SPL for the A80. [wens@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: DRAM initialisation for sun9iPhilipp Tomsich2016-10-30-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-10-29-0/+27
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| * arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+3
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See2016-10-27-0/+6
| | | | | | | | | | | | | | | | | | | | Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-10-28-108/+65
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| * | board: sama5d2_xplained: Enable an early debug UARTWenyou Yang2016-10-28-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable an early debug UART to debug problems when an ICE or other debug mechanism is not available. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | board: sama5d2_xplained: Set 'ethaddr' got from AT24MACWenyou Yang2016-10-28-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | If 'ethaddr' is not set, we will get the ethernet address from AT24MAC, and set it to 'ethaddr' variable. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Songjun Wu <songjun.wu@microchip.com> Reviewed-by: Andreas Bießmann <biessmann@corscience.de>
| * | board: sama5d2_xplained: Clean up codeWenyou Yang2016-10-28-104/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the introduction of pinctrl and clk driver, and the dts file, remove unneeded the pin configurations and the clock enabling code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | board: sama5d2_xplained: Move config options to defconfigsWenyou Yang2016-10-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Move the config options from the include/configs/sama5d2_xplained.h to configs/sama5d2_xplained_*_defconfig. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm, at91: add icache supportHeiko Schocher2016-10-28-6/+0
| |/ | | | | | | | | | | | | | | | | | | | | add at least icache support for at91 based boards. This speeds up NOR flash access on an at91sam9g15 based board from 15.2 seconds reading 8 MiB from a SPI NOR flash to 5.7 seconds. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-28-18/+889
|\ \ | |/ |/| | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
| * imx6: icorem6: Add NAND supportJagan Teki2016-10-26-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support for Engicam i.CoreM6 qdl board. Boot Log: -------- U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43) Trying to boot from NAND NAND : 512 MiB U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 55C Reset cause: WDOG Model: Engicam i.CoreM6 DualLite/Solo Starter Kit DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> Cc: Scott Wood <oss@buserror.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/DualJagan Teki2016-10-26-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.CoreM6 Quad/Dual modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DQ, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * engicam: icorem6: Add DM_GPIO, DM_MMC supportJagan Teki2016-10-26-70/+72
| | | | | | | | | | | | | | | | | | | | | | Add DM_GPIO, DM_MMC support for u-boot and disable for SPL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/SoloJagan Teki2016-10-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.CoreM6 DualLite/Solo modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DL, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx: s/docs\/README.imximage/doc\/README.imximage/gJagan Teki2016-10-26-15/+15
| | | | | | | | | | | | | | | | | | | | Fixed typo for doc/README.imximage on respective imximage.cfg files. Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: icorem6: Add ENET supportJagan Teki2016-10-26-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add enet support for engicam icorem6 qdl starter kit. - Add pinmux settings - Add board_eth_init TFTP log: -------- Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> tftpboot {fdt_addr} imx6dl-icore.dtb Using FEC device TFTP from server 192.168.2.96; our IP address is 192.168.2.75 Filename 'imx6dl-icore.dtb'. Load address: 0x0 Loading: ###### 1.3 MiB/s done Bytes transferred = 28976 (7130 hex) CACHE: Misaligned operation at range [00000000, 00007130] icorem6qdl> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial supportJagan Teki2016-10-26-0/+455
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Log for i.CoreM6 DualLite/Solo Starter Kit: ----------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 31C Reset cause: POR DRAM: 256 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device switch to partitions #0, OK mmc0 is current device reading boot.scr ** Unable to read file boot.scr ** reading zImage 6741808 bytes read in 341 ms (18.9 MiB/s) Booting from mmc ... reading imx6dl-icore.dtb 30600 bytes read in 19 ms (1.5 MiB/s) Booting using the fdt blob at 0x18000000 Using Device Tree in place at 18000000, end 1800a787 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 Boot Log for i.CoreM6 Quad/Dual Starter Kit: -------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6Q rev1.2 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Reset cause: POR DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx: mx6ullevk: correct boot device macroPeng Fan2016-10-24-2/+2
| | | | | | | | | | | | | | | | Correct boot device macro according to kconfig entry in common/Kconfig Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6ullevk: support pluginPeng Fan2016-10-24-1/+140
| | | | | | | | | | | | | | | | Add plugin code for mx6ullevk. Define CONFIG_USE_IMXIMG_PLUGIN in defconfig file to use plugin code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * mx6sabresd: Add README fileDiego Dorta2016-10-17-0/+103
| | | | | | | | | | | | | | | | | | Add a README to explain the steps for booting mx6sabresd in different ways: 1. Booting via Normal U-Boot (u-boot.imx) 2. Booting via SPL (SPL and u-boot.img) 3. Booting via Falcon mode (SPL launches the kernel directly) Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
| * mx6sabresd: Add Falcon mode supportDiego Dorta2016-10-17-0/+12
| | | | | | | | | | | | | | | | Allow i.MX6Q Sabre SD to load the kernel and dtb via SPL in Falcon mode. Based on the Falcon mode code for MX6 Gateworks Ventana board. Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
| * nitrogen6x: add secure boot supportGary Bisson2016-10-17-0/+18
| | | | | | | | | | | | | | | | Declaring a CSF section makes the imximage tool increase the size of data to be loaded by the BootROM and also adds a pointer to that CSF section in the IVT header to the BootROM can check the signature. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
* | video: Move video_get_info_str() prototype to a header fileSimon Glass2016-10-23-0/+4
| | | | | | | | | | | | | | | | This should be defined in a header file so that arguments are checked. Move it to video.h. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Convert CONSOLE_PRE_CONSOLE_BUFFER options to KconfigSimon Glass2016-10-23-0/+3
| | | | | | | | | | | | | | Move these option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | arm: Provide common PSCI based reset handlerAlexander Graf2016-10-19-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: Disable HVC PSCI calls by defaultAlexander Graf2016-10-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-10-15-10/+221
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| * pbl: use "wait" command instead of "flush" commandZhao Qiang2016-10-14-8/+4
| | | | | | | | | | | | | | | | | | | | PBL flush command is restricted to CCSR memory space. So use WAIT PBI command to provide enough time for data to get flush in target memory. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> [York Sun: rewrap commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * Txxx/RCW: Split unified RCW to RCWs for sd, spi and nand.Zhao Qiang2016-10-14-2/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | T series boards use unified RCW for sd, spi and nand boot. Now split txxx_rcw.cfg to txxx_sd_rcw.cfg, txxx_spi_rcw.cfg and txxx_nand_rcw.cfg for SPI/NAND/SD boot. And modify RCW[PBI_SRC] for them: PBI_SRC=5 for SPI 24-bit addressing PBI_SRC=6 for SD boot PBI_SRC=14 for IFC NAND boot Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://git.denx.de/u-boot-fdtTom Rini2016-10-13-1/+1
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| * cmd/fdt: add possibilty to have 'extrasize' on fdt resizeHannes Schmelzer2016-10-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes devicetree nodes and or properties are added out of the u-boot console, maybe through some script or manual interaction. The devicetree as loaded or embedded is quite small, so the devicetree has to be resized to take up those new nodes/properties. In original the devicetree was only extended by effective 4 * add_mem_rsv. With this commit we can add an argument to the "fdt resize" command, which takes the extrasize to be added. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Acked-by: Simon Glass <sjg@chromium.org>
* | board: am335x: Always set eth/eth1addr environment variableRoger Quadros2016-10-13-26/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | Ethernet ports might be used in the kernel even if CPSW driver is disabled at u-boot. So always set ethaddr and eth1addr environment variable from efuse. Retain usbnet_devaddr as it is required for SPL USB eth boot. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | board: am335x-icev2: add ethernet phy mode detection logicRoger Quadros2016-10-13-7/+75
|/ | | | | | | | | | | | | | | | | | | Both ethernet ports can be used as CPSW ethernet (RMII mode) or PRU ethernet (MII mode) by setting the jumper near the port. Read the jumper value and set the pinmux, external mux and PHY clock accordingly. As jumper line is overridden by PHY RX_DV pin immediately after bootstrap (power-up/reset), we have to use GPIO edge detection to capture the jumper line status. As u-boot doesn't provide any infrastructure for GPIO edge detection, we directly access the GPIO registers. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-10-12-0/+23
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| * x86: conga-qeval20-qa3: Add README to explain the console UART optionsStefan Roese2016-10-11-0/+23
| | | | | | | | | | | | | | | | | | This patch adds a small README to explain the 2 defconfig files and its usage for the different console UART options. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-10-12-0/+514
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| * | arm: kirkwood: fix Synology board tagWalter Schweizer2016-10-09-0/+7
| | | | | | | | | | | | | | | Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: kirkwood: fix output enable settingsWalter Schweizer2016-10-09-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: kirkwood: fix kirkwood initial setupWalter Schweizer2016-10-09-11/+16
| | | | | | | | | | | | | | | Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: kirkwood: ds109 board is maintainedWalter Schweizer2016-10-09-0/+6
| | | | | | | | | | | | | | | Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-10-28 10:40:21 +0000