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| * | sunxi: make SoC variant choice mandatoryChen-Yu Tsai2016-05-25-1/+0
| |/ | | | | | | | | | | | | | | | | The user should always select an SoC variant to support. Not choosing one doesn't make sense for a bootloader. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-25-2/+7
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| * powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDBYing Zhang2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5, FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6. Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/t208xrdb: Update MAINTAINERS fileYork Sun2016-05-19-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc/t208xqds: Update MAINTAINERS fileYork Sun2016-05-19-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-38/+48
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| * | armv8: ls1043ardb: invert irq pin polarity for AQR105 PHYShaohui Xie2016-05-18-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043ardb: fix types of variablesQianyu Gong2016-05-18-3/+3
| | | | | | | | | | | | | | | | | | | | | Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043a: remove redundant code in board filesQianyu Gong2016-05-18-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043ardb: fix the limitation of using 'cpld reset'Qianyu Gong2016-05-18-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: uniform usage of u32 in ls102x caam configVincent Siles2016-05-18-1/+1
| | | | | | | | | | | | | | | | | | | | | Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: Fix SCFG ICID reg addressesVincent Siles2016-05-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Update MAINTAINERS filePrabhakar Kushwaha2016-05-17-2/+2
| | | | | | | | | | | | | | | | | | | | | Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls2080ardb: Update DDR timing to support more UDIMMsShengzhou Liu2016-05-17-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-16/+8
| |/ | | | | | | | | | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-05-24-13/+75
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| * | ARM: zynq: Simplify zynq configurationMichal Simek2016-05-24-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extending Kconfig for adding new platform is a lot of work for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and remove all dependencies on TARGET_ZYNQ_* options including SPL. As a side-effect it also remove custom init folder for ps7_init_gpl.* files. Folder is chosen based on device-tree file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Add SPL support supportMichal Simek2016-05-24-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Add support for reading MAC from eepromMichal Simek2016-05-24-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for on board eeprom with programmed MAC for using in u-boot to have uniq address for every board. Most of the time uniq MAC address is on a label on the board. If address is not programmed use these command to program it. On zcu102: ZynqMP> mm.b 0 00000000: 00 ? 00 00000001: a0 ? 0a 00000002: 35 ? 35 00000003: 02 ? 02 00000004: 00 ? ef 00000005: 00 ? 67 00000006: 00 ? q i2c dev 5 i2c write 0 54 20 6 i2c md 54 20 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-05-24-2/+318
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| * | | board: sama5d2_xplained: change SDHCI GCK's clock source to UPLLWenyou Yang2016-05-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the clock source of the SDHCI's generated clock from PLLA to UPLL clock to align to Linux driver. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | board: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0Wenyou Yang2016-05-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the missing pin config of the SDMMC0 interface. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | board: atmel: add SAMA5D2 PTC Engineering boardWenyou Yang2016-05-24-0/+315
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-23-0/+100
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| * | x86: galileo: Override SMBIOS product nameBin Meng2016-05-23-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Override the default product name U-Boot reports in the SMBIOS table, to be compatible with the Intel provided UEFI BIOS, as Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of it to do different board level configuration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: baytrail: Add .gitignore for ACPI enabled boardsBin Meng2016-05-23-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Let git ignore dsdt.aml, dsdt.asl.tmp and dsdt.c files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: baytrail: Enable ACPI table generation for all boardsBin Meng2016-05-23-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ACPI table generation by creating a DSDT table for all baytrail boards: conga-qeval20-qa3-e3845, bayleybay and minnowmax. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-23-1/+262
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| * | | malta: Remove ".set mips32" directivePaul Burton2016-05-21-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We always build for a mips32 or higher ISA, so this ".set mips32" directive is redundant. Once MIPSr6 support is added it will become harmful since some instruction encodings change & this directive will cause the older encodings to be incorrectly emitted instead of the appropriate ones for the build. In preparation for supporting MIPSr6, remove this redundant directive. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | mips: ath79: Add support for TPLink WDR4300Marek Vasut2016-05-21-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the TPLink WDR4300 router, which is based on the AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported on this system as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * | | mips: ath79: add AP143 reference boardWills Wang2016-05-21-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add board-level code and base DT for AP143. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | mips: ath79: add AP121 reference boardWills Wang2016-05-21-0/+73
| |/ / | | | | | | | | | | | | | | | | | | | | | This patch add board-level code and base DT for AP121. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | compulab: add support for layout aware eeprom commandsNikita Kiryanov2016-05-20-0/+344
|/ / | | | | | | | | | | | | | | | | Add layout definitions and implement functions for field printing/updating, layout detection, layout assignment, and layout parsing. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-17-4/+11
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| * | dm: usb: Drop the get_dev() functionSimon Glass2016-05-17-1/+1
| | | | | | | | | | | | | | | | | | This function is implemented by the legacy block functions now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSISimon Glass2016-05-17-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This option currently enables both the command and the SCSI functionality. Rename the existing option to CONFIG_SCSI since most of the code relates to the feature. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: sandbox: Add a board for sandbox without CONFIG_BLKSimon Glass2016-05-17-0/+7
| |/ | | | | | | | | | | | | | | While the driver-model block device support is in progress, it is useful to build sandbox both with and without CONFIG_BLK. Add a separate board for the latter. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: fsl_i2c: Rename I2C register structuremario.six@gdsys.cc2016-05-17-13/+15
|/ | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* arm: socfpga: Update iomux and pll for c5 socdk RevEDinh Nguyen2016-05-10-36/+36
| | | | | | Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-3/+3
| | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* ARM: tegra: import latest Jetson TK1 spreadsheetStephen Warren2016-05-04-1/+14
| | | | | | | | | | | | | | | This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Fix spelling of "occurred".Vagrant Cascadian2016-05-02-3/+3
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Change my mailaddressAndreas Bießmann2016-05-02-6/+6
| | | | | | I'll switch my mails to my own server, so drop all gmail references. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: DRA7: Add ABB setup for all domainsNishanth Menon2016-04-25-0/+3
| | | | | | | | | | | | | ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon2016-04-25-0/+1
| | | | | | | | | | | ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: hikey: Simplify README instructions.Peter Griffin2016-04-25-46/+49
| | | | | | | | | | | | | | This patch updates and simplifies the hikey README. The old instructions were hard to follow, and convoluted. This patch also updates the link to the mcuimage.bin which was outdated. Using an outdated mcuimage.bin results in the additional a53 cores not coming online when the kernel issues PSCI requests to arm trusted firmware (ATF). Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: hisilicon: hikey: Align memory node with upstream kernelPeter Griffin2016-04-25-1/+29
| | | | | | | | | | | | | | | The memory node gets automatically generated by U-Boot in arch_fixup_fdt(), before passing control to the kernel using U-Boots representation of the dram banks. However the upstream kernel uses the memory node to carve-out regions of RAM for various purposes. To make this work without changing arch_fixup_fdt() which will effect many platforms we replicate the upstream memory node layout using the dram banks. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: hisilicon: hikey: Implement reset_cpu() for hikey.Peter Griffin2016-04-25-2/+2
| | | | | | | | | | | | | | | This allows the reset command to reset the board from u-boot. => reset resetting ... INFO: BL1: 0xf9810000 - 0xf9818000 [size = 32768] NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.1(debug):7fb9b0e NOTICE: BL1: Built : 17:06:41, Apr 19 2016 Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.Peter Griffin2016-04-25-0/+3
| | | | | | | | | | | Currently only the serial pl01x driver is using DT, and the other drivers still use platform data but as more DT lands in the upstream kernel the aim is to migrate the other drivers over to DT as well to have a fully DT configured hikey u-boot. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-14 15:57:47 +0000