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* ppc4xx: New board avnet fx12 minimodulGeorg Schardt2008-10-24-0/+157
| | | | | | | | | | This patch adds support for the avnet fx12 minimodul. It needs the "ppc4xx: Generic architecture for xilinx ppc405" patch from Ricardo. Signed-off-by: Georg Schardt <schardt@team-ctech.de> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Generic architecture for xilinx ppc405(v3)Ricardo Ribalda Delgado2008-10-24-0/+459
| | | | | | | | | | | | | | | | | As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
* mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov2008-10-21-4/+2
| | | | | | | | | | With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-21-0/+44
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov2008-10-21-0/+123
| | | | | | | | | | This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix serdes setup for the MPC8378E boardsAnton Vorontsov2008-10-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | MPC837xE specs says that SerDes1 has: — Two lanes running x1 SGMII at 1.25 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. And for SerDes2: — Two lanes running x1 PCI Express at 2.5 Gbps; — One lane running x2 PCI Express at 2.5 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. The spec also explicitly states that PEX options are not valid for the SD1. Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX, which is wrong to do. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: mpc8360emds: rework LBC SDRAM setupAnton Vorontsov2008-10-21-12/+27
| | | | | | | | | | | | | | | | | | | Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-0/+477
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| * ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setupStefan Roese2008-10-21-0/+12
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add GDSys neo 405EP board supportDirk Eibach2008-10-21-0/+308
| | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | TQM8260: environment in flash instead EEPROM, baudrate 115kWolfgang Denk2008-10-21-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Several customers have reported problems with the environment in EEPROM, including corrupted content after board reset. Probably the code to prevent I2C Enge Conditions is not working sufficiently. We move the environment to flash now, which allows to have a backup copy plus gives much faster boot times. Also, change the default console initialization to 115200 bps as used on most other boards. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | 85xx: Fix compile warning in mpc8536ds.cKumar Gala2008-10-21-1/+0
| | | | | | | | | | | | | | mpc8536ds.c: In function 'is_sata_supported': mpc8536ds.c:615: warning: unused variable 'devdisr' Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-77/+77
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Use strmhz() to format clock frequenciesWolfgang Denk2008-10-21-10/+13
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge git://git.denx.de/u-boot into x1Markus Klotzbuecher2008-10-21-10980/+11855
|\ \ | |/ | | | | | | | | Conflicts: drivers/usb/usb_ohci.c
| * Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+42
| | | | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+48
| | | | | | | | | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| * Make pixis_set_sgmii more general to support MPC85xx boards.Liu Yu2008-10-18-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
| * mpc8572 additional end-point modeEd Swarthout2008-10-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0. Include host_agent == 0 decode for end-point determination. This is not needed for the ds reference board since pcie3 will be a host in order to connect to the uli chip. Include it here as a reference for other mpc8572 boards. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| * pixis do not print long help if not configuredEd Swarthout2008-10-18-0/+4
| | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| * Add DDR options setting on MPC8641HPCN boardHaiying Wang2008-10-18-36/+110
| | | | | | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| * Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-28/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| * Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-21/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| * 85xx: Improve flash remapping on MPC8572DS & MPC8536DSKumar Gala2008-10-18-14/+10
| | | | | | | | | | | | | | | | Changing the flash from cacheable to cache-inhibited was taking a significant amount of time due to the fact that we were iterating over the full 256M of flash. Instead we can just flush the L1 d-cache and invalidate the i-cache. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mgcoge, mgsuvd: extract more common codeHeiko Schocher2008-10-18-90/+56
| | | | | | | | | | | | | | | | in ft_blob_update () for both boards was an unneccessary repetition of code, which this patch moves in a common function for this boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgcoge, mgsuvd: use in_*/out_* accesorsHeiko Schocher2008-10-18-4/+6
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgsuvd: fix compiler warning when using soft_i2c driverHeiko Schocher2008-10-18-1/+2
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgsuvd: fix coding styleHeiko Schocher2008-10-18-38/+29
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgcoge: Second Flash on CS5 not on CS1Heiko Schocher2008-10-18-1/+1
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-10720/+10720
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * mgcoge, mgsuvd: added support for the IVM EEprom.Heiko Schocher2008-10-18-0/+302
| | | | | | | | | | | | | | | | The EEprom contains some Manufacturerinformation, which are read from u-boot at boot time, and saved in same hush shell variables. Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgcoge, mgsuvd: add board specific I2C deblocking mechanism.Heiko Schocher2008-10-18-2/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As documented in doc/I2C_Edge_Conditions, adding a board specific deblocking mechanism via CFG_I2C_INIT_BOARD for the mgcoge and mgsuvd board. This code was originally written by Keymile in association with Anatech and Atmel in 1998. The Code toggels the SCL until the SCA line goes to HIGH (max. 16 times). And after this, a start condition is sent. This is another approach to deblock the I2C Bus. The soft I2C driver actually sends 9 clocks with SDA High, and then a stop at the end, to deblock the I2C Bus. Maybe we should use the approach from Keymile as the new standard? Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgcoge, mgsuvd: add I2C support.Heiko Schocher2008-10-18-2/+23
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgcoge: fix Coding Style issues.Heiko Schocher2008-10-18-41/+38
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * mgsuvd, mgcoge: move this 2 boards in one dir.Heiko Schocher2008-10-18-0/+6
| | | | | | | | | | | | | | | | There are some more extensions, which are for both boards and some more boards from this manufacturer will follow soon. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Fix compiler warning in lib_ppc/board.cHeiko Schocher2008-10-15-1/+1
| | | | | | | | | | | | | | Fix compiler warning introduced by commit 0f8cbc18 Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Do not init SATA when disabled on 8536DS.Jason Jin2008-10-14-0/+12
| | | | | | | | | | | | | | | | | | | | SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the driver still try to access the SATA registers, the cpu will hangup. This patch try to fix this by reading the serdes status before the SATA initialize. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl_diu: fix alignment error that caused malloc corruptionNikita V. Youshchenko2008-10-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When aligning malloc()ed screen_base, invalid offset was added. This not only caused misaligned result (which did not cause hardware misbehaviour), but - worse - caused screen_base + smem_len to be out of malloc()ed space, which in turn caused breakage of futher malloc()/free() operation. This patch fixes screen_base alignment. Also this patch makes memset() that cleans framebuffer to be executed on first initialization of diu, not only on re-initialization. It looks correct to clean the framebuffer instead of displaying random garbage; I believe that was disabled only because that memset caused breakage of malloc/free described above - which no longer happens with the fix described above. Signed-off-by: Nikita V. Youshchenko <yoush@debian.org>
| * ARM DaVinci: Remove redundant setting of GD_FLG_RELOC for sffsdr board.Hugo Villeneuve2008-10-13-4/+0
| | | | | | | | | | | | | | This is no longer necessary now that the GD_FLG_RELOC flag is set for all ARM boards. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
| * Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-10-13-9/+9
| |\
| | * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-12-1/+1
| | |\
| | | * FSL: Fix get_cpu_board_revision() return value.Rafal Czubak2008-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_cpu_board_revision() returned board revision based on information stored in global static struct eeprom. It should instead use one from local struct board_eeprom, to which the data is actually read from EEPROM. The bug led to system hang after printing L1 cache information on U-Boot startup. The problem was observed on MPC8555CDS system and possibly affects other Freescale MPC85xx boards using CFG_I2C_EEPROM_CCID. The change has been successfully tested on MPC8555CDS system. Signed-off-by: Rafal Czubak <rcz@semihalf.com>
| | * | mpc83xx: spd_sdram: fix ddr sdram base address assignment bugAnton Vorontsov2008-09-24-8/+8
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | ppc4xx: Fix USB 2.0 phy reset sequenceMatthias Fuchs2008-10-10-3/+32
| | | | | | | | | | | | | | | | | | | | | This patch fixes USB 2.0 communication issues on some DU440 boards. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add strapping mode for 667MHz CPU frequency on DU440 boardMatthias Fuchs2008-10-10-0/+6
| | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix DU440 GPIO configurationMatthias Fuchs2008-10-10-5/+5
| |/ | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Canyonlands: Remove unnecessary FDT warning upon DTB fixupStefan Roese2008-09-22-12/+4
| | | | | | | | | | | | | | | | | | Depending on the configuration jumper "SATA SELECT", U-Boot disabled either one PCIe node or the SATA node in the device tree blob. This patch removes the unnecessary and even confusing warning, when the node is not found at all. Signed-off-by: Stefan Roese <sr@denx.de>
| * socrates: fix crash after relocationAnatolij Gustschin2008-09-22-1/+1
| | | | | | | | | | | | | | | | | | | | Currently U-Boot crashes after relocation to RAM. Changing the CPO value of the DDR SDRAM TIMING_CFG_2 register to READ_LAT + 1 (to the value it was before conversion of socrates to new DDR code) fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * sh: Fix compile warningNobuhiro Iwamatsu2008-09-19-24/+39
| | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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