| Commit message (Collapse) | Author | Age | Lines |
| |
|
|\
| |
| |
| | |
Code cleanup.
|
| | |
|
| |\
| | |
| | |
| | |
| | |
| | |
| | | |
Rewrite of NAND code based on what is in 2.6.12 Linux kernel
Patch by Ladislav Michl, 29 Jun 2005
[Merge with /home/tur/nand/u-boot]
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for
NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is
implemented for these boards.
|
| | |
| | |
| | |
| | | |
Patch by Stefan Roese, 4 Mar 2006
|
| | |
| | |
| | |
| | | |
Patch by Stefan Roese, 1 Mar 2006
|
| | |
| | |
| | |
| | | |
Patch by Stefan Roese, 28 Feb 2006
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
* Add env-variable "unlock" to handle initial state of sectors
(locked/unlocked).
Only the U-Boot image and it's environment is protected,
all other sectors are unprotected (unlocked) if flash
hardware protection is used (CFG_FLASH_PROTECTION) and
the environment variable "unlock" is set to "yes".
Patch by Stefan Roese, 28 Feb 2006
* Update drivers/cfi_flash.c:
- find_sector() called in both versions of flash_write_cfiword()
Patch by Peter Pearse, 27th Feb 2006
* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
Patch by Jose Maria Lopez, 16 Jan 2006
* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
* Changes/fixes for drivers/cfi_flash.c:
We *should* check if there are any error bits if the previous call
returned ERR_OK (Otherwise we will have output an error message in
flash_status_check() already.) The original code would only check for
error bits if flash_status_check() returns ERR_TIMEOUT.
Patch by Marcus Hall, 23 Aug 2005
* Changes/fixes for drivers/cfi_flash.c:
- Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
- Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
Patch by Sangmoon Kim, 19 Aug 2005
* Fixes for drivers/cfi_flash.c:
- Fix wrong timeout value usage in flash_status_check()
- Round write_tout up when converting to msec in flash_get_size()
- Remove clearing flash status at the end of flash_write_cfibuffer()
which sets Intel 28F640J3 flash back to command mode on CSB472
Patch by Tolunay Orkun, 02 July 2005
|
| | | |
|
| | |
| | |
| | |
| | | |
Minimally modified patch by Bluetechnix, Vienna
|
| | |
| | |
| | |
| | | |
Controller.
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
* For READ_STATUS and READID commands always 8 bytes need to be read from
NDDB. Otherwise they stay there and get send to flash as the first data
word when writing.
* In nand_base.c the oob variable is not reset so this->oob_buf is
overwritten what eventually screws up the bad block descriptor table.
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
* Debug message can be turned on and off.
* Waiting for events now times out.
* Implemented RESET command.
* Added appropriate nand_bbt_descriptor and nand_oobinfo.
Remaining Problems:
* Read Status still behaves weird an returns invalid stuff sometimes.
* ECC Placement does not respect our scheme in nand_oobinfo.
|
| | |
| | |
| | |
| | | |
don't ask me why. There are still bugs in the bad block logic.
|
| | |
| | |
| | |
| | | |
after all.
|
| | |
| | |
| | |
| | | |
start at an offset of 4 bytes from the start of the page.
|
| | | |
|
| | |
| | |
| | |
| | |
| | | |
delta_cmdfunc function, because this bit is only set once after a command
is sent and this allows read functions to be called multiple times.
|
| | |
| | |
| | |
| | | |
there are 0)
|
| | | |
|
| | | |
|
| | | |
|
|\ \ \
| | |/
| |/|
| | | |
This is a first version of the testing-NAND branch merged back to main.
|
| |\ \ |
|
| | | |
| | | |
| | | |
| | | | |
Patch by Ladislav Michl, 13 Sep 2005
|
|\ \ \ \
| | |_|/
| |/| | |
|
| | | |
| | | |
| | | |
| | | | |
Patch by Reinhard Arlt, 8 Feb 2006
|
| |/ /
| | |
| | |
| | | |
Patch by Matthias Fuchs, 07 Feb 2006
|
| | | |
|
| | |
| | |
| | |
| | | |
we only see 64MB.
|
| | | |
|
| | |
| | |
| | |
| | | |
zylonite). Minor pxa-regs.h update.
|
| | | |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
* lots of bugfixes in the assembler code
* reverted hardware.h back to original
* enabled hardware DRAM calibration
* GCC-4 fix: modified GLOBAL_DATA_POINTER macro
|
|/ / |
|
| |
| |
| |
| | |
Patch by Stefan Roese, 18 Jan 2006
|
| |
| |
| |
| |
| |
| | |
Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
Patch by Reinhard Arlt, 30 Dec 2005
|
| |
| |
| |
| |
| |
| | |
PMC405 and CPCI2DP: Added firmware download and booting via pci.
Patch by Matthias Fuchs, 20 Dec 2005
|
| |
| |
| |
| | |
(without bank-switching only 32 MB can be accessed)
|
| | |
|
| |
| |
| |
| | |
Patch by Eugen Bigz, 19 Dec 2005
|
| |
| |
| |
| |
| |
| |
| |
| | |
- Changed GPIO setup to enable another address line in order to
address 64M of FLASH.
- Added function sdram_tr1_set to auto calculate the tr1 value for
the DDR.
Patch by Steven Blakeslee, 12 Dec 2005
|
| | |
|
| | |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
- Support for TQM8541/8555 boards added.
- Complete rework of TQM8540/8560 support.
- Common TQM85xx code now supports all current TQM85xx platforms
(TQM8540/8541/8555/8560).
- DDR SDRAM size detection added.
- CAS latency default values can be overwritten by setting "serial#"
to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
If problems are detected with this non default CAS latency,
the defualt values will be used instead.
- FLASH size detection added.
- Moved FCC ethernet driver initialization behind TSEC driver init
-> TSEC is first device.
Patch by Stefan Roese, 30 Nov 2005
|
| |
| |
| |
| | |
Patch by John Otken, 23 Nov 2005
|
| |
| |
| |
| | |
Patch by Stefan Roese, 27 Nov 2005
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
On PPC44x platforms, the startup message generated in "cpu.c" only
comprised the ppc type and revision but not additional informations
like speed etc. Those speed infos where printed in the board specific
code. This new implementation now prints all CPU infos in the common
cpu specific code. No board specific code is needed anymore and
therefore removed from all current 44x implementations.
Patch by Stefan Roese, 27 Nov 2005
|
| |
| |
| |
| |
| |
| |
| | |
- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
- CFG_FLASH_QUIET_TEST added to use the common CFI driver
for bank autodetection
Patch by Stefan Roese, 22 Nov 2005
|