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* spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-1/+1
| | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: spi: rename tegra SPI driversAllen Martin2013-03-25-1/+1
| | | | | | | | | Rename tegra SPI drivers to tegra20_flash and tegra20_slink in preparation for commonization and addition of tegra114_spi. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* tegra: remove support for UART SPI switchAllen Martin2013-03-25-130/+1
| | | | | | | | | | This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* am335x_evm: Add better timings for the new BeagleBoard DDR3 partTom Rini2013-03-24-1/+38
| | | | | Tested-by: Rao Bodapati <rao@circuitco.com> Signed-off-by: Tom Rini <trini@ti.com>
* ti814x_evm: add ti814x evm board supportMatt Porter2013-03-24-0/+302
| | | | | | | | | | Add TI814X EVM board directory, config file, and MAINTAINERS entry. Enable build. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt to recent omap_hsmmc requirements, Matt re-tested] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: refactor emif4/ddr to support multiple EMIF instancesMatt Porter2013-03-24-4/+4
| | | | | | | | | | The AM33xx emif4/ddr support closely matches what is need to support TI814x except that TI814x has two EMIF instances. Refactor all the emif4 helper calls and the config_ddr() init function to use an additional instance number argument. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* am33xx: convert defines from am33xx-specific to generic namesMatt Porter2013-03-24-6/+6
| | | | | | | | Eliminate AM33xx specific names to prepare for TI814x support within AM33xx-land. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* am335x: Enable DDR PHY dynamic power down bit for DDR3 boardsVaibhav Hiremath2013-03-24-2/+4
| | | | | | | | | | | | | Enable DDR PHY dynamic power down bit, which enables powering down the IO receiver when not performing read. This also helps in reducing overall power consumption in low power states (suspend/standby). Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* cm-t35: add support for loading splash image from NANDNikita Kiryanov2013-03-22-0/+61
| | | | | | | Add support for loading splash image from NAND Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* ARM: rpi_b: enable SD controller, add related env/cmdsStephen Warren2013-03-20-0/+26
| | | | | | | | | | | Enable the SD controller driver for the Raspberry Pi. Enable a number of useful MMC, partition, and filesystem-related commands. Set up the environment to provide standard locations for loading a kernel, DTB, etc. Provide a boot command that loads and executes boot.scr.uimg from the SD card; this is written considering future extensibilty to USB storage. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: rpi_b: use bcm2835 mbox driver to get memory sizeStephen Warren2013-03-20-1/+20
| | | | | | | | | | | The firmware running on the bcm2835 SoC's VideoCore CPU determines how much of the system RAM is available for use by the ARM CPU. Previously, U-Boot assumed that only 128MB was available, since this was the smallest value configured by any public firmware. However, we can now query the actual value at run-time from the firmware using the mbox property protocol. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-03-18-0/+63
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| * arm:trats: Use new ums commandLukasz Majewski2013-03-18-0/+63
| | | | | | | | | | | | | | | | | | This patch enables new "ums" command on Trats board Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-03-18-1978/+4349
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting. Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h Build tested for all of ARM and run-time tested on am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-500/+1092
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| | * Tegra114: Dalmore: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: fdt: Move aliases from dtsi to dts file as per other TegrasTom Warren2013-03-14-0/+8
| | | | | | | | | | | | | | | | | | | | | All other Tegra boards have their alias nodes in the .dts file Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bitsTom Warren2013-03-14-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmux code issues a warning if the caller attempts to disable the lock bit in a pinmux register, since this is impossible (once it's locked, the only way to unlock it is to reset the device/pmt controller). The I2C/DDC/CEC/USB macros expect a lock setting to be passed in, and the previous setting of DISABLE caused the pinmux table parsing code to issue the warning. Changing the lock bits in these table entries to DEFAULT (i.e. don't touch it) fixes this. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routinesTom Warren2013-03-14-1/+81
| | | | | | | | | | | | | | | | | | | | | T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)Tom Warren2013-03-14-0/+15
| | | | | | | | | | | | | | | | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: Cardhu: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 initTom Warren2013-03-14-180/+286
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: Cardhu: Remove unneeded cardhu.c.mmc fileTom Warren2013-03-14-151/+0
| | | | | | | | | | | | | | | | | | | | | | | | This was an older debug/developmental file that got added accidentally. Not needed/used in any Cardhu build. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)Tom Warren2013-03-14-0/+5
| | | | | | | | | | | | | | | | | | | | | Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: Remove memreserve line from Cardhu/Seaboard DT filesTom Warren2013-03-14-2/+0
| | | | | | | | | | | | | | | | | | | | | Not used, and wrong in Cardhu's case Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: MMC: Add DT support to MMC driver for all T20 boardsTom Warren2013-03-14-145/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT filesTom Warren2013-03-14-8/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux dts files were used for those boards that didn't already have sdhci info populated. Tamonten has their own dtsi file with common sdhci nodes (sourced from Linux). Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: tamonten: Add common tamonten.dtsi file from linuxTom Warren2013-03-14-3/+492
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra: fdt: Change /include/ to #include for C preprocessorTom Warren2013-03-14-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | dts Makefile has the arch & board include paths added to DTS_CPPFLAGS. This allows the use of '#include "xyz"' in the dts/dtsi file which helps the C preprocessor find common dtsi include files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * Tegra114: fdt: Update DT files with I2C info for T114/DalmoreTom Warren2013-03-14-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * tegra: usb: move implementation into right directoryLucas Stach2013-03-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the Tegra USB implementation into the drivers/usb/host directory. Note that this merges the old /arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code changes, just moving stuff around. v2: While at it also move some defines and the usb.h header file to make usb driver usable for Tegra30. NOTE: A lot more work is required to properly init the PHYs and PLL_U on Tegra30, this is just to make porting easier and it does no harm here. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-274/+2342
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| | * nitrogen: Use unsigned long to specify the total RAM sizefabio.estevam@freescale.com2013-03-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building for the nitrogen boards with 2GiB the following warning happens: nitrogen6x.c:89:38: warning: integer overflow in expression [-Woverflow] 2GiB can not fit in 32-bits, so use ulong instead. Reported-by: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * Add Boundary Devices Nitrogen6X boardsEric Nelson2013-03-13-0/+2039
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * mx23_olinuxino: Fix warning for implicit declarationOtavio Salvador2013-03-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes a build warning of implicit declaration of gpio_direction_output, as bellow: ,---- | mx23_olinuxino.c: In function 'board_early_init_f': | mx23_olinuxino.c:51:2: warning: implicit declaration | of function 'gpio_direction_output' | [-Wimplicit-function-declaration] `---- Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mx6: Provide a structure for accessing HDMI registersFabio Estevam2013-03-07-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | Provide a structure for accessing HDMI registers, so that we can use proper read/write accessors. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * mx23_olinuxino: Enable USB supportOtavio Salvador2013-03-07-0/+9
| | | | | | | | | | | | | | | | | | This enabled USB support for the mx23_olinuxino board. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mx23_olinuxino: Add support for status LEDOtavio Salvador2013-03-07-0/+11
| | | | | | | | | | | | | | | | | | | | | This allow user to know if the bootloader is running, even without a serial console. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mx23evk: Adjust DRAM control register to use full 128MB of RAMOtavio Salvador2013-03-07-0/+10
| | | | | | | | | | | | | | | | | | | | | Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full 128MB of RAM. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mxs: m28: Enable power to USB port 0Marek Vasut2013-03-07-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB port 0 can now be used alongside the USB port 1, thus enable power to it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * i.MX6: consolidate pad names for multi-CPU boardsEric Nelson2013-03-07-215/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename all i.MX6 pad declarations to MX6_PAD_x, so a board may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo (MX6DL) by including the proper header. Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd only support MX6Q, so they include mx6q_pins.h. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6: mx6qsabrelite: indent with tabsEric Nelson2013-03-07-53/+53
| | | | | | | | | | | | | | | | | | | | | This patch has no functional changes and simply replaces leading spaces with tabs. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2013-03-05-1004/+0
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| | * \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2013-02-23-8235/+4349
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| | * | | imx: mx6q DDR3 init: Benefit from available CL = 7Benoît Thébaudeau2013-02-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it. In these conditions: tRCD(min) = 13.125 ns tRP(min) = 13.125 ns tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns tRAS(min, DDR3-1600K) = 35 ns MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0]. MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18]. MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0]. MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29]. MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26]. MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | | imx: mx6q DDR3 init: Fix MR0.PPDBenoît Thébaudeau2013-02-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | | imx: mx6q DDR3 init: Fix RST_to_CKEBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | | imx: mx6q DDR3 init: Fix SDE_to_RSTBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | | imx: mx6q DDR3 init: Fix tXPRBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR. For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD). Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * | | imx: mx6q DDR3 init: Fix tMRDBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns) Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
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