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* udoo: Add a README fileFabio Estevam2016-10-06-0/+21
| | | | | | | Add a README file to explain how to build and flash the SD card for Udoo boards. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* pcm052: add new BK4r1 target based on PCM052 SoMAlbert ARIBAUD \(3ADEV\)2016-10-06-52/+136
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* pcm052: allow specifying onboard DDR size in configsAlbert ARIBAUD \(3ADEV\)2016-10-06-0/+4
| | | | | | | | | | PCM052 SoMs may be equipped with various sizes of DDR. Keep default of 256MB; new PCM052-based targets will specify their actual DDR size. Linux command line is auto-adjusted to DDR size. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* pcm052: add 'm4go' commandAlbert ARIBAUD \(3ADEV\)2016-10-06-0/+38
| | | | | | | Add the 'm4go' command to pcm052-based targets. It loads scatter file images. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* arm: imx: add i.MX6ULL 14x14 EVK board supportPeng Fan2016-10-04-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6ULL EVK board support: Add device tree file, which is copied from NXP Linux. Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR. The uart iomux settings are still keeped in board file. Boot Log: U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800) CPU: Freescale i.MX6ULL rev1.0 at 396MHz CPU: Commercial temperature grade (0C to 95C) at 15C Reset cause: POR Model: Freescale i.MX6 ULL 14x14 EVK Board Board: MX6ULL 14x14 EVK DRAM: 512 MiB MMC: initialized IMX pinctrl driver FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1 is current device Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* mx6sabresd: Make SPL DDR configuration to match the DCD tableFabio Estevam2016-10-04-154/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. This causes stability issues like the ones reported at 7dbda25ecd6d7c ("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also: http://lists.denx.de/pipermail/u-boot/2016-September/266355.html . As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Retrieved the DCD tables from: board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg and board/freescale/mx6sabresd/mx6qp.cfg (NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga) This method makes it easier for people converting from non-SPL to SPL code. Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* wandboard: Fix hang when going into low frequencyFabio Estevam2016-10-04-3/+3
| | | | | | | | | | | | | | A kernel hang is observed when running wandboard 3.14 kernel and going to the lowest operational point of cpufreq: # ifconfig eth0 down # echo 1 > /sys/class/graphics/fb0/blank The problem is caused by incorrect setting of the REFR field of register MDREF. Setting it to 4 refresh commands per refresh cycle fixes the hang. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-10-03-152/+8
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| * rockchip: add boot-mode support for rk3288, rk3036Jacob Chen2016-10-01-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | rockchip platform have a protocol to pass the the kernel reboot mode to bootloader by some special registers when system reboot. In bootloader we should read it and take action. We can only setup boot_mode in board_late_init becasue "setenv" need env setuped. So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init" to replace "board_late_init" in board file. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: move common function from board-file to rk3036-board.cJacob Chen2016-10-01-132/+0
| | | | | | | | | | | | | | To keep it same with 3288 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: miniarm: remove eMMC supportXu Ziyuan2016-10-01-8/+0
| | | | | | | | | | | | | | The latest rk3288-miniarm board doesn't have eMMC device, so remove it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: evb_rk3399: init vdd_center regulatorKever Yang2016-10-01-0/+6
| | | | | | | | | | | | | | | | Add vdd_center pwm regulator get_device to enable this regulator. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | board: am33xx-hs: Allow post-processing of FIT image on AM33xxAndrew F. Davis2016-10-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | When CONFIG_FIT_IMAGE_POST_PROCESS or CONFIG_SPL_FIT_IMAGE_POST_PROCESS is enabled board_fit_image_post_process will be called, add this function to am33xx boards when CONFIG_TI_SECURE_DEVICE is set to verify the loaded image. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | board: ks2: Enable ECC using detected DDR sizeLokesh Vutla2016-10-01-0/+3
|/ | | | | | | | | EEC is being enabled based on the ddr size populated by SPD data. But not all keystone platforms have SPD data to detect ddr3 size. So, enable ECC using the detected DDR size. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-09-30-33/+33
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/dra7xx_evm.h
| * usb: fsl: Rename fdt_fixup_dr_usbSriram Dash2016-09-27-33/+33
| | | | | | | | | | | | | | | | The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-09-27-1/+7
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| * | ARM: tegra: fix ULPI PHY on Ventana and SeaboardStephen Warren2016-09-27-1/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana. Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arm64: mvebu: Add Armada 7K db-88f7040 development board supportStefan Roese2016-09-27-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell Armada 7K DB-88F7040 development board. Supported are the following interfaces: - UART - SPI (incl. SPI NOR) - I2C - USB - SATA / AHCI Support for other interfaces will follow. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | arm64: mvebu: Add Armada 3700 db-88f3720 development board supportStefan Roese2016-09-27-0/+147
|/ | | | | | | | | | | | | | | | | | | This patch adds basic support for the Marvell Armada 3700 DB-88F3720 development board. Supported are the following interfaces: - UART - SPI (incl. SPI NOR) - I2C - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-427/+2011
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun2016-09-26-3/+51
| | | | | | | | | | | | | | | | | | Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-14-4/+1084
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046ardb: Add LS1046ARDB board supportMingkai Hu2016-09-14-0/+751
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-348/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-14-1/+6
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-14-1/+34
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-13/+0
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+24
| | | | | | | | | | | | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+28
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set individual device access permissionHou Zhiqiang2016-09-14-14/+20
| | | | | | | | | | | | | | | | Add this API to make the individual device is able to be set to the specified permission. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-14-32/+0
| | | | | | | | | | | | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: ls1043ardb: move sec_init to board_initSumit Garg2016-09-14-15/+17
| | | | | | | | | | | | | | | | | | | | sec_init() which was earlier called in misc_init_r() is now done in board_init() before PPA init as SEC block will be used during PPA image validation. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | board: amcore: update to use dm serial driverAngelo Dureghello2016-09-25-1/+14
| | | | | | | | | | | | | | | | | | Update amcore board to use dm serial driver. Signed-off-by: Angelo Dureghello <angelo@sysam.it> --- Changes for v2: - None
* | arm: mvebu: add DB-88F6820-AMC boardChris Packham2016-09-24-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is a plug in card for Marvell's switch system development kits. Form-factor aside it is similar to the DB-88F6820-GP with the following differences. - TCLK is 200MHz - SPI1 is used - No SATA - No MMC - NAND flash Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: theadorable: Configure board for PCIe 2.0 capabilityStefan Roese2016-09-24-0/+6
| | | | | | | | | | | | | | | | Use a board-specific board_sat_r_get() function to configure the board for PCIe 2.0 capability (e.g. 5GB/s link speed). Otherwise the default of 2.5GB/s will be established. Signed-off-by: Stefan Roese <sr@denx.de>
* | treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-70/+70
| | | | | | | | | | | | | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* | treewide: use #include <...> to include public headersMasahiro Yamada2016-09-23-2/+2
| | | | | | | | | | | | | | | | | | We are supposed to use #include <...> to include headers in the public include paths. We should use #include "..." only for headers in local directories. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arch, board: squash lines for immediate returnMasahiro Yamada2016-09-23-43/+11
| | | | | | | | | | | | | | | | Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Angelo Dureghello <angelo@sysam.it>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-09-22-1/+43
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| * | board: evb-rk3399: enable usb 2.0 host vbus power on board_initKever Yang2016-09-22-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | rk3399 using one gpio control signal for two usb 2.0 host port, it's better to enable the power in board file instead of in usb driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rk3399: enable the pwm2/3 pinctrl in board initKever Yang2016-09-22-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no interrupt line for each PWM which used by pinctrl to get the periph_id, so it's not able to enable the default pinctrl setting by pinctrl framework, let's enable it at board_init(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-09-22-4/+124
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| * | | ARM64: zynqmp: Add support for chip ID detectionMichal Simek2016-09-22-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chip ID needs to be known for loading bitstream because U-Boot checks ID from bitstream header in BIT format. BIN format is completely unchecked. The chipid is get from ATF via SMC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add support for DFU from SPLMichal Simek2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL needs to have bigger stack size because of USB. Simple malloc needs to be disabled because dfu code requires different allocation functions. There is no space in OCM that's why random place in DDR is used. BOOTD must be disabled because it is causing compilation error. All variables are disabled and used only variables valid for DFU because they are simple huge. Including automatic variables added by CONFIG_ENV_VARS_UBOOT_CONFIG. Hardcode addresses for u-boot, atf, kernel and dtb just for SPL DFU code. Enable SPL DFU for zcu100. Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Fix usb_gadget_handle_interrupt routineMichal Simek2016-09-22-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Function is defined in g_dnl.h and have different parameter then it is used. This patch fixes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Wire up both USBs available on ZynqMPMichal Simek2016-09-22-2/+18
| |/ / | | | | | | | | | | | | | | | The second USB wasn't enabled. This patch fixes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-09-21-6/+297
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| * | boston: Introduce support for the MIPS Boston development boardPaul Burton2016-09-21-0/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces support for building U-Boot to run on the MIPS Boston development board. This is a board built around an FPGA & an Intel EG20T Platform Controller Hub, used largely as part of the development of new CPUs and their software support. It is essentially the successor to the older MIPS Malta board. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Malta: Enable CM & L2 supportPaul Burton2016-09-21-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for the MIPS Coherence Manager & L2 caches on the MIPS Malta board, removing the need for us to attempt to bypass the L2 during boot (which would fail with recent CPUs that expose L2 config via the CM anyway). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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