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* EXYNOS: support TRATS board display functionDonghwa Lee2012-05-15-0/+146
| | | | | | | | | This patch support TRATS board configuration and display function. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* SMDK5250: fix compiler warningMinkyu Kang2012-05-15-1/+1
| | | | | | | | | this patch fixed following warning. tzpc_init.c: In function 'tzpc_init': tzpc_init.c:35: warning: assignment from incompatible pointer type Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Chander Kashyap <chander.kashyap@linaro.org>
* misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998Łukasz Majewski2012-05-15-17/+10
| | | | | | | | TRATS target uses MAX8997 PMIC device instead of MAX8998. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurementŁukasz Majewski2012-05-15-3/+22
| | | | | | | | | | | | | | This patch enables LDO4 power line for preparing proper voltages to be measured by ADC converter. This measurement is used for determination of target board HW revision. Test HW: Universal_C210 (Exynos4210) rev. 0.0 Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS: Rename exynos5_tzpc structure to exynos_tzpcChander Kashyap2012-05-15-1/+1
| | | | | | | | | | | TZPC IP is common across Exynos based SoC'c. Renaming exynos5_tzpc in arch/arm/include/asm/arch-exynos/tzpc.h to exynos_tzpc will allow generic usase of tzpc. Also modify board/samsung/smdk5250/tzpc_init.c to use exynos_tzpc. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INITNobuhiro Iwamatsu2012-05-15-2/+2
| | | | | | | | | | With almost all the architecture and board BOARD_LATE_INIT does not use. CONFIG_BOARD_LATE_INIT is used instead. This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* cm-t35: add I2C multi-bus supportNikita Kiryanov2012-05-15-0/+6
| | | | | | | Enable I2C multi-bus support and config I2C muxes for I2C2 and I2C3. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* omap3: Introduce weak misc_init_rTom Rini2012-05-15-40/+0
| | | | | | | | | | | | | Introduce a __weak misc_init_r function that just runs dieid_num_r(). Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was all they did for misc_init_r. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* omap730p2: Remove empty misc_init_rTom Rini2012-05-15-6/+0
| | | | | | We had a do-nothing misc_init_r, remove along with CONFIG_MISC_INIT_R Signed-off-by: Tom Rini <trini@ti.com>
* omap5912osk: Remove empty misc_init_rTom Rini2012-05-15-7/+0
| | | | | | We had a do-nothing misc_init_r, remove along with CONFIG_MISC_INIT_R Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: pandora: revise GPIO configurationGrazvydas Ignotas2012-05-15-13/+41
| | | | | | | | | | | | Update pandora's GPIO setup code with these changes: - convert to gpiolib - set up dual voltage GPIOs to match supply of 1.8V by clearing VMODE1 - add GPIO_IO_PWRDNZ configuration for DM3730 variation of pandora (required to enable GPIO 126, 127, and 129 I/O cells in DM3730) - add wifi reset pulse as recommended by wifi chip's manufacturer - drop configuration of GPIOs that u-boot doesn't need Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
* OMAP3: pandora: pin mux updates for DM3730 board variantGrazvydas Ignotas2012-05-15-0/+9
| | | | | | | DM3730 needs some additional pin mux configuration for GPIOs 126-129 to work, add it. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
* power: twl6035: add palmas PMIC supportSRICHARAN R2012-05-15-3/+3
| | | | | | palmas/TWL6035 is power IC for omap5 evm boards Signed-off-by: Balaji T K <balajitk@ti.com>
* OMAP5: board: Add pinmux data for omap5_evm board.SRICHARAN R2012-05-15-230/+259
| | | | | | Adding the full pinmux data for OMAP5430 sevm board. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP3: igep00x0: Reduce lines of code for IGEP-based boards.Enric Balletbò i Serra2012-05-15-4/+0
| | | | | | | | | | | | | | This is rework on config files of IGEP-based boards with the aim to remove duplicated code to be more maintainable. Basically this patch creates a common configuration file for both boards and only sets the specific option in the board config file. On board files the hardcored mach type was replaced in favour of using the CONFIG_MACH_TYPE option. More than 200 duplicated lines have been deleted. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
* OMAP4460: TPS Ensure SET1 is selected after voltage configurationNishanth Menon2012-05-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM:OMAP+:MMC: Add parameters to MMC initJonathan Solnit2012-05-15-26/+26
| | | | | | | | | | Add parameters to the OMAP MMC initialization function so the board can mask host capabilities and set the maximum clock frequency. While the OMAP supports a certain set of MMC host capabilities, individual boards may be more restricted and the OMAP may need to be configured to match the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example. Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
* kirkwood: add support for Cloud Engines Pogoplug E02David Purdy2012-05-15-0/+374
| | | | | | | | | | | This patch adds support for Cloud Engines Pogoplug E02 Information regarding the CE Pogoplug E02 board can be found at: http://archlinuxarm.org/platforms/armv5/pogoplug-v2-pinkgray Signed-off-by: Dave Purdy <david.c.purdy@gmail.com> Cc: prafulla@marvell.com Cc: albert.u.boot@aribaud.net
* kirkwood: add NAS62x0 board supportLuka Perkov2012-05-15-0/+331
| | | | | | | | | | | | | | | Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. NAS6210 has 1 SATA and 1 eSATA port while NAS6220 has 2 SATA ports. More information about the boards can be found here: http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7036 http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7515 Signed-off-by: Luka Perkov <uboot@lukaperkov.net> Signed-off-by: Gerald Kerma <dreagle@doukki.net> Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
* devkit3250: add Timll DevKit3250 board initial supportVladimir Zapolskiy2012-05-15-0/+109
| | | | | | | | | | | This change adds a basic support for Embest/Timll DevKit3250 board, NOR and UART are the only supported peripherals for a moment. The board doesn't require low-level init, because the initial SDRAM and GPIO configuration is performed during kickstart bootloader execution. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingWolfgang Denk2012-04-30-1/+1
|\ | | | | | | | | | | | | | | | | | | * 'agust@denx.de' of git://git.denx.de/u-boot-staging: lin_gadget: use common linux/compat.h linux/compat.h: rename from linux/mtd/compat.h lin_gadget: use common mdelay gunzip: rename z{alloc, free} to gz{alloc, free} fs/fat: align disk buffers on cache line to enable DMA and cache part_dos: align disk buffers on cache line to enable DMA and cache
| * linux/compat.h: rename from linux/mtd/compat.hMike Frysinger2012-04-30-1/+1
| | | | | | | | | | | | This lets us use it in more places than just mtd code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2012-04-30-229/+391
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ppc4xx: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
| * | powerpc/ppc4xx: Remove typedefs for gdsys FPGADirk Eibach2012-04-30-20/+22
| | | | | | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20Dirk Eibach2012-04-30-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | In hardware revision 1.20 one more fan controller is added to dlvision-10g. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changesDirk Eibach2012-04-30-37/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | Print fpga info at last_stage_init on gdsys 405ep boards. Use dtt_init() to startup fans. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | powerpc/ppc4xx: Make gdsys 405ep boards reset more genericDirk Eibach2012-04-30-172/+293
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | In order to add boards that have different hardware for fpga reset, any 405ep gdsys board now provides these functions: void gd405ep_init(void); void gd405ep_set_fpga_reset(unsigned state); void gd405ep_setup_hw(void); int gd405ep_get_fpga_done(unsigned fpga); Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-04-30-57/+52
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot cmd_bdinfo: display the address map size (32-bit vs. 36-bit) PowerPC: correct the SATA for p1/p2 rdb-pc platform powerpc/corenet_ds: Slave core in holdoff when boot from SRIO powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO powerpc/corenet_ds: Slave uploads ucode when boot from SRIO powerpc/corenet_ds: Slave module for boot from SRIO powerpc/corenet_ds: Master module for boot from SRIO powerpc/corenet_ds: Document for the boot from SRIO powerpc/corenet_ds: Correct the compilation errors about ENV powerpc/srio: Rewrite the struct ccsr_rio powerpc/85xx:Fix lds for nand boot debug info powerpc/p2041rdb: add env in NAND support powerpc/p2041rdb: add NAND and NAND boot support powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards powerpc/85xx:Avoid vector table compilation for nand_spl powerpc/85xx:Fix IVORs addr after vector table relocation powerpc/85xx:Avoid hardcoded vector address for IVORs powerpc/p1023rds: Disable nor flash node and enable nand flash node
| * | powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during bootTimur Tabi2012-04-24-52/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/corenet_ds: Slave uploads ucode when boot from SRIOLiu Gang2012-04-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * | powerpc/corenet_ds: Slave module for boot from SRIOLiu Gang2012-04-24-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * | powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boardsYork Sun2012-04-24-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p1023rds: Disable nor flash node and enable nand flash nodeChunhe Lan2012-04-24-0/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the p1023rds, when system boots from nor flash, kernel only accesses nor flash and can not access nand flash with BR0/OR0; when system boots from nand flash, kernel only accesses nand flash and can not access nor flash with BR0/OR0. Default device tree nor and nand node should have the following structure: Example: nor_flash: nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x02000000>; bank-width = <2>; device-width = <1>; status = "okay"; partition@0 { label = "ramdisk"; reg = <0x00000000 0x01c00000>; }; } nand_flash: nand@1,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p1023-fcm-nand", "fsl,elbc-fcm-nand"; reg = <0x2 0x0 0x00040000>; status = "disabled"; u-boot-nand@0 { /* This location must not be altered */ /* 1MB for u-boot Bootloader Image */ reg = <0x0 0x00100000>; read-only; }; } When booting from nor flash, the status of nor node is enabled and the status of nand node is disabled in the default dts file, so do not do anything. But, when booting from nand flash, need to do some operations: o Disable the NOR node by setting status = "disabled"; o Enable the NAND node by setting status = "okay"; Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | board/adp-ag102: add board specific filesMacpaul Lin2012-04-22-0/+150
|/ | | | | | Add board specific files. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2012-04-18-1/+1
|\ | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-sh: sh: ecovec: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT sh: Fix rsk7264 pin setup for on-board ethernet
| * sh: Fix rsk7264 pin setup for on-board ethernetPhil Edworthy2012-04-18-1/+1
| | | | | | | | | | | | | | This sets up the external ethernet IRQ pin. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | i.MX6: arm2: Add AXI cache and Qos settingDirk Behme2012-04-17-0/+6
|/ | | | | | | | | | | | | | | Do the same AXI cache and Qos settings done already in the SabreLite imximage.cfg for the ARM2 board, too. It fixes a display flash issue caused by low priority of the display IDMA channel. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com> Acked-by: Jason Liu <r64343@freescale.com>
* Prepare v2012.04-rc2; minor Coding Style cleanupWolfgang Denk2012-04-16-28/+28
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MX35: mx35pdk: wrong board revisionStefano Babic2012-04-16-11/+0
| | | | | | | | | | | | | | | | | | | The board revision is detected accessing to the pmic, that is not available before relocation (I2C). This generates the following error: CPU: Freescale i.MX35 rev 2.0 at 532 MHz. Reset cause: WDOG <reg num> = 7 is invalid. Should be less than 0 Board: MX35 PDK 1.0 The revision number is wrong, as a default value is printed (tested on a mx35pdk Rev. 2.0). Move the output in the board_late_init(), when pmic can be accessed. Signed-off-by: Stefano Babic <sbabic@denx.de>
* MX31: mx31pdk: drop enable_caches from board fileStefano Babic2012-04-16-8/+0
| | | | | | | | | enable_caches() is implemented now in cpu.c for ARM1136. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX53: DDR: Fix ZQHWCTRL field TZQ_CSTroy Kisky2012-04-16-4/+4
| | | | | | | | | Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x02 - 128 cycles. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* cm-t35: fix Ethernet reset timingIgor Grinberg2012-04-16-5/+6
| | | | | | | | | | | The reset_net_chip() function has wrong timings for the reset pulse. This appeared to work until: 0607e2b (ARMV7: OMAP: Write more than 1 byte at a time in i2c_write) Fix the Ethernet support by introducing right timings. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* BeagleBoard: Remove userbutton command and use gpio command insteadJoel Fernandes2012-04-16-55/+0
| | | | | | | Remove userbutton command and do the detection in board config file using the gpio command Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com> Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
* Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2012-04-09-4/+50
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-net: net/designware: Change timeout loop implementation net/designware: Set ANAR to 0x1e1 net/designware: Program phy registers when auto-negotiation is ON net/designware: Try configuring phy on each dw_eth_init net/designware: Consecutive writes must have delay net/designware: Phy address fix net/designware: Fix the max frame length size net/designware: Fix to restore hw mac address microblaze: Wire up LL_TEMAC driver initialization microblaze: Add faked LL_TEMAC driver configuration microblaze: Enable several ethernet driver compilation net: ll_temac: Add LL TEMAC driver to u-boot Update net subsystem maintainer in doc/git-mailrc net/eth.c: fix eth_write_hwaddr() to use dev->enetaddr as fall back mvgbe: remove warning for unused methods
| * microblaze: Wire up LL_TEMAC driver initializationStephan Linz2012-04-04-0/+36
| | | | | | | | | | | | | | Initialize ll_temac driver. Reported-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Stephan Linz <linz@li-pro.net>
| * microblaze: Add faked LL_TEMAC driver configurationStephan Linz2012-04-04-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Expand the specific configuration for the microblaze-generic board in xparameters.h with a faked setup to enable the LL_TEMAC driver. Note: From now the microblaze-generic board is no longer a valid board configuration for a real piece of hardware. Rather than, we use the file config.mk and xparameters.h as a faked board configuration to force the compilation of all potential driver code for Microblaze systems. Signed-off-by: Stephan Linz <linz@li-pro.net>
* | Merge branch 'master' of git://git.denx.de/u-boot-onenandWolfgang Denk2012-04-09-0/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-onenand: onenand: samsung: Enable OneNAND support at Samsung's Exynos4210 onenand: Replace ONENAND_IS_MLC() with ONENAND_HAS_4KB() onenand:samsung OneNAND chip probe functions added for GONI and Exynos4210 onenand:samsung Target dependent OneNAND chip probe function
| * | onenand:samsung OneNAND chip probe functions added for GONI and Exynos4210Lukasz Majewski2012-04-04-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | Separate callback for probing OneNAND memory chip. Tested at: Samsung S5PC110 GONI Samsung Exynos4210 (S5PC210 Universal) Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
* | x86: Remove dead code in eNETSimon Glass2012-04-01-5/+0
|/ | | | | | | This avoids a compiler warning about unused variables. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-By: Graeme Russ <graeme.russ@gmail.com>
* pci: get rid of local prototypesLinus Walleij2012-03-30-8/+0
| | | | | | | | two boards were redeclaring pciauto_region_allocate() in their local scope for no obvious reason, the function is in <pci.h> anyway, this is probably just copying artifacts and old cruft. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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