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* ENGR00153394 mx50 rd3: make SDHC1 as default boot device for androidXinyu Chen2011-07-20-0/+6
| | | | | | | Drop NAND/SPI boot support. Enable fastboot. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00152755 MX6 Switch DRAM init script from plugin to DCD for emmc fastbootAnish Trivedi2011-07-06-263/+140
| | | | | | | | | | | | | | | | | ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot mode is to be used. Therefore, switched the DRAM script from plugin to DCD table. The DCD table created is based on the following RVD script: Arik_init_DDR3_528MHz_002.inc found at http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845 When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not get reset when RSTA bit is set by uboot driver. Therefore, need to write 0 to it manually during driver init. This brings USDHC out of fastboot mode, allowing normal communication with emmc to proceed in uboot. Changed comments for DLL delay to be more accurate. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00139206 MX6 USDHC eMMC 4.4 supportAnish Trivedi2011-07-05-4/+17
| | | | | | | | | | | New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00152439: MX51: PLL workaround should be implemented only for PLL1Ranjani Vaidyanathan2011-07-01-2/+15
| | | | | | Make sure the PLL workaround is done only for PLL1. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00139198: iMX61 uBoot add ENET supportZeng Zhaoming2011-06-27-1/+3
| | | | | | | | | | | | | | | | Add ENET and AR8031 PHY support to uboot. To make it works on sabreauto, need do following changes: 1. rework phy to output 125M clock from CLK_25M signal, and the 125M clock input to SoC as reference clock to generate RGMII_TXC clock. 2. Enable TXC delay in PHY debug register. 3. set ENET working in RMII mode. 4. set ENET working at 1000M or 100M/10M. 5. set ENET TX fifo to maximum to avoid underrun error. 6. force AR8031 PHY working at 100M Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-0/+961
| | | | | | | | | | | | | Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00151966: MX51 - Apply SW workaround for the PLL1 unlock HW issue.Ranjani Vaidyanathan2011-06-22-10/+43
| | | | | | | | | | | | | | | | | | | | | | Apply the following SW workaround to fix the PLL unlock issue. 1.Move all the clock sources which are currently running on PLL1 from PLL1 to PLL2 2.Clear AREN bit in PLL1 (to avoid restart during MFN change) 3.Program the PLL1 to the next settings: a. MFI = 8 b. MFD = 179 c. MFN = 180 d. PLM = 1 4.Manually restart the PLL1 5.Wait to PLL1 to lock 6.Reprogram the PLL1 to the next settings: a. MFI = 60, others keep same 7.Load the MFN 8.Wait for LDREQ and delay ~4.6us 9.Switch the clocks which were previously moved from PLL1 to PLL2 back to PLL1 Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00151892 MX50: Workaround to prevent PLL1 from losing lockAnish Trivedi2011-06-21-24/+59
| | | | | | | | | | | | | | | PLL1 workaround to prevent it from losing lock: (1) Disable AREN bit to avoid PLL1 restart during MFN change (2) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179, PDF = 0 (3) Manual restart PLL1 (4) Wait PLL1 lock (5) Set PLL1 to 800Mhz with only change MFN to 60, others keep (6) Set LDREQ bit to load new MFN (7) Poll on LDREQ bit for MFN update to be completed (8) Delay at least 4 us to avoid PLL1 instability window (9) Switch ARM back to PLL1 Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00151187 MX53 SMD: Kernal stopped Usb driver after reseting in stop modeWayne Zou2011-06-10-1/+14
| | | | | | | After reseting in stop mode, the VUSB_2V5 voltage is disable by pmic. It needs to be enable manually in u-boot. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00144224: MX53: Add MMU mapping for all peripheralsTerry Lv2011-06-09-36/+84
| | | | | | | Not all peripherals are mapped in MMU. Thus we add those missed mapped area. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00144389 mx53 QS Ripley: change VCC from 1.35V to 1.3V QS Ripley boardWayne Zou2011-06-01-2/+2
| | | | | | Change VCC from 1.35V to 1.3V QS Ripley board Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00143837 mx50 rd3: support android boot from RD3 NAND deviceXinyu Chen2011-05-23-4/+2
| | | | | | | | | Enable NAND gpio, recovery mode detect after boot from spi nor. Change default env for loading kernel and uramdisk from NAND, disabling elcdif lcd driver to support EPDC eink panel as default. Enable recovery mode support and NAND/UBI/UBIFS command. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00143302 Add mc34708 pmic support on loco/Ripley boardZou Weihua -wayne zou2011-05-20-10/+47
| | | | | | Add mc34708 pmic support on loco/Ripley board Signed-off-by: Zou Weihua -wayne zou <b36644@freescale.com>
* ENGR00143461 mx51 evk: increase VDDGP as 1.1v for 800MHZLily Zhang2011-05-16-0/+5
| | | | | | | | The default VDDGP output voltage is 1.05V in mx51 evk board According to mx51 datasheet (Rev 0.4), the VDDGP for 800MHZ should be 1.1v for 800MHZ Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00143457: Don't let ROM copy .bss sectionJason Liu2011-05-16-5/+9
| | | | | | | | | | | Don't need let ROM copy the .bss section since it will all be zeroed by u-boot at start up, thus it can speed up the boot up time. Need add CONFIG_FLASH_HEADER_OFFSET to the size since ROM will copy from the beginning of the MMC card. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00143442 uboot: support android spi boot and mfg on mx50 rd3 boardXinyu Chen2011-05-16-3/+97
| | | | | | | | | | | | Add mx50_rd3_android default config file Add basic support for UBI partition mount and UBIFS file read for recovery Add gpmi nand enable in MFG kernel commandline by uboot configure, which enable MFG tool to flash system images on NAND. The total NAND boot and NAND recovery has been disabled. They will be enabled later. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00143428 mx53 ard RevB: use internal clock for sataLily Zhang2011-05-14-0/+19
| | | | | | Switch to use SATA internal clock in mx53 ARD RevB board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR modeAnish Trivedi2011-05-10-0/+15
| | | | | | | | | | | | | | | | | | On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller. By default eSDHC is selected. However, eSDHC shows some borderline timing in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode at 50 MHz. Therefore, add a compile time option to uboot for MX50 to select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port. By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR, is commented out in the include/configs/mx50_<board>.h file to select eSDHC with DDR mode enabled. Uncomment the define to select uSDHC with only SDR mode enabled. Also increased max frequency supported by ESDHC to 52 MHz instead of 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00142497 Android: MX53_SMD: check eMMC and SD recovery file.Zhang Jiejing2011-04-22-38/+42
| | | | | | | | | | Check eMMC and SD cards recovery file, if it exist, enter recovery mode. original code only check SD card, since we already change main storage to eMMC, so we check it both, since most of customer still test it under SD card, check them to avoid support effert. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00142322: mx53-smd: spi nor: can't erase 0x200000 sizeTerry Lv2011-04-20-1/+1
| | | | | | | | | | | | | Spi nor can't erase 0x200000 size. There are two issues in this CR. 1. Spi nor can't erase 0x200000 size. 2. Whole chip erase don't work. The solution will be: 1. Delay more time for WIP check. 2. Use normal erase for whole chip erase. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00142259 set UART2_RXD (GP6_11) to highRobby Cai2011-04-18-0/+10
| | | | | | | Isolate EIM signals and boot configuration signals. Without this setting, the chip's temperature will be high. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00142247 MX50: Add PD+3 routine for all DDR typesRobby Cai2011-04-16-18/+34
| | | | | | | | | | | PD+3 routine help test pass for ddr with higher freq. Tested on ARM2 board (mDDR, DDR2) RDP board (LPDDR2 from both vendors) RD3 board (LPDDR2) Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00142246 MX50 Update DDR2 script to use more optimized settingsRobby Cai2011-04-16-123/+64
| | | | | | | | | | | | | | | New DDR2 initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_DDR2_266MHz.inc v3, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Also corrected the DDR clock. (DDR mode changed from Sync to Async) Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00141335-3: Add CONFIG_EMMC_DDR_PORT_DETECT to mx53 and mx50config filesTerry Lv2011-04-11-0/+6
| | | | | | | | | | | | Add CONFIG_EMMC_DDR_PORT_DETECT to mx53 and mx50 config files. For fastboot, please note that the bit width of card should match the dip settings. For example, if mmcinfo shows eMMC 4.4 card is 8Bit DDR, then dip settings should be 8bit DDR. Then fastboot can work. Otherwise, fastboot will fail. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141556: Fix copyright issueTerry Lv2011-04-08-7/+4
| | | | | | | | | | | We're following the following rules: 1. FSL copyright should be added for freescale added and modified files. 2. FSL copyright should go after existing copyrights. 3. For Duplicate FSL copyright, Our copyright will go after that also. 4. FSL copyright should not include personal names as part. 5. For only FSL copyright, "All rights reserved" is not mattered. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141410 MX50 RD3: Set GPIO4_16 to Enable DCDC_3V15Robby Cai2011-03-31-2/+12
| | | | | | | | This is needed for FEC to work properly, since FEC3V15 is supplied by DCDC_3V15. In addition, corrected the pin name for FEC_EN. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00141363: change mx53 uart clk parent to pll2Jason Chen2011-03-31-22/+47
| | | | | | | | | | Change all mx53 platform uart clk default parent to pll2. MX53 SMD board need support LVDS and HDMI at the same time, they may use the same clock parent-pll4, so kernel need change ipu di clock parent to pll3, after that, uart clock parent need change to pll2 to avoid console mess. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00141129: Add m25p32 spi_nor support for mx53_smdTerry Lv2011-03-24-0/+81
| | | | | | Add m25p32 spi_nor support for mx53_smd. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141000 MX50_RDP: add android recovery support.Zhang Jiejing2011-03-23-0/+118
| | | | | | Add android recovery related config and code. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00140537 mx53: update vddgp according to new data sheetZhou Jingyu2011-03-23-0/+33
| | | | | | mx53: update vddgp according to new data sheet Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140982 MX53 Increase VDDGP to 1.25V for 1 GHzAnish Trivedi2011-03-22-6/+6
| | | | | | | | MX53 TO 2.0 requires 1.25V for VDDGP instead of 1.2V in order for the core to operate at 1 GHz. Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140872 Add MX50 RD3 SupportRobby Cai2011-03-22-10/+60
| | | | | | | | Assembled With new PMIC chip - MC34708 (Ripley), and new SPI NOR - M25P32 as well. Add new config file for RD3. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00140825: Add mx53 to2.1 chip id recognitionTerry2011-03-20-4/+17
| | | | | | Add mx53 to2.1 chip id recognition. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140692 Update for DDR3-based MX53 SABRE Auto boardsMahesh Mahadevan2011-03-16-4/+102
| | | | | | | Added a new config file, the DDR setup is similar to the MX53 Quick Start & MX53 SABRE-Tablet ref design boards. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00139747: Read fuse to distinguish between mx53 revA and revBTerry Lv2011-03-02-7/+36
| | | | | | | | | Read fuse to distinguish between mx53 revA and revB. Now SoC efuse is used for board id. Thus we now check fuse value for board rev and id. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139924 mx53 smd &loco: set bootup vdd GP to 1.2vZhou Jingyu2011-03-01-0/+6
| | | | | | set bootup vdd GP to 1.2v for mx53 smd &loco Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00138689 MX50 Update LPDDR2 script to use more optimized settingsAnish Trivedi2011-01-31-315/+42
| | | | | | | | | | | | | | | | New LPDDR2 initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_LPDDR2_266MHz.inc v7, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Also removed ARM2 LPDDR2 init section since the settings for that board are the same as the RDP (EVK). Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00138635 MX50 Update mDDR script to use more optimized settingsAnish Trivedi2011-01-28-55/+55
| | | | | | | | | | | | | New mDDR (LPDDR1) initialization script from designer includes controller changes as well as very important PHY changes that increase internal sampling window to detect DQS edge. This increase compensates for possible jitter. The script, Codex_LPDDR1_200MHz.inc v4, is found at http://compass.freescale.net/livelink/ livelink?func=ll&objId=218722501&objAction=browse&viewType=1 Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00138148 MX53 TO2.0 EVK: change the default core as 1GHZLily Zhang2011-01-18-9/+18
| | | | | | | Change the default core frequency as 1GHZ for MX53 TO2.0 EVK board Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00138040-3 Protect splashimage related stuffs by configLiu Ying2011-01-17-3/+5
| | | | | | | This patch protects splashimge related stuffs by config option for mx51 bbg, mx53 ard and mx53 smd. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137552 MX53: increase VDDGP as 1.2V for 1GHZLily Zhang2011-01-15-3/+30
| | | | | | | | | The norminal voltage of VDDGP for 1GHZ is 1.2V in MX53 TO2.0 datasheet (RevD). So set the CPU frequency as 800MHZ firstly since VDDGP is 1.1V after power on. After increasing VDDGP as 1.2V, increase CPU as 1GHZ. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137894-6 MX53 SMD:Support splashimageLiu Ying2011-01-14-1/+127
| | | | | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 20KHz and the pwm duty is 50%. Only lvds panel is supported. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. However, only lvds1 is tested as the lvds cable cannot be plugged into lvds0 connector. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-5 MX53 ARD:Support splashimageLiu Ying2011-01-14-0/+207
| | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 200Hz and the pwm duty is 50%. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-4 IPUv3 FB: IPUv3 FB driver enhancementLiu Ying2011-01-14-3/+6
| | | | | | | | 1) Change MX51 related function names to IPUv3 related names. 2) Change MX51 related comments to IPUv3 related comments. 3) Do not set panel_info.cmap to be NULL pointer. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137791 MX53: Update for MFG toolLily Zhang2011-01-11-8/+1
| | | | | | | | - Add MFG tool support for MX53 SMD and MX53 LOCO boards - Update mx53 ARD MFG defconfig to pass compile Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137766 BBG splashimage:Allocate cmap for panel_infoLiu Ying2011-01-10-1/+10
| | | | | | | This patch allocates cmap for panel_info, otherwise, cmap_base in common/lcd.c will be NULL pointer. Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-4/+24
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137642 MX53 Uboot Align DDR3 script for Loco and SMD boardsAnish Trivedi2011-01-05-4/+4
| | | | | | | | | | | | | Changed the value of one register, offset 0x88, of the ESDCTL controller to match the official script for the boards, entitled "MX53_TO2_DDR3_LCB.inc", found at http://compass.freescale.net/livelink/livelink/221435668/ MX53_TO2_DDR3_LCB.inc.txt?func=doc.Fetch&nodeid=221435668 The register value sets read delay lines. The change is minor. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00137497-2 MX53: Add LOCO board supportLily Zhang2010-12-30-0/+1202
| | | | | | | | | | | Add MX53 LOCO board support The following functions are tested in the board: - Micro SD boot - MMC/SD read/write. - clk command - fuse command Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00136075 MX53: Add SMD board supportLily Zhang2010-12-30-0/+1236
| | | | | | | | | | | | | | | | | | | | | | | Add MX53 SMD support: - Use DDR3 script for SMD board from Mike Kjar: "Rita_init_LCB_CMOS.inc" - Set the default CPU core frequency as 1GHZ. The following functions are tested on SMD board: - SD/MMC boot, read, write via SDHC1 - eMMC4.4 boot, read, write via SDHC3. - SATA boot, read, write. To support SATA boot via internal clock, please ensure the fuse "SATA_ALT_CLK_REF" was blown. - FEC - UART - clk command - iim command Signed-off-by: Liu Ying <b17645@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
generated by cgit v1.1 at 2024-11-22 05:34:51 +0000