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* mpc8xx: remove lwmon board supportMasahiro Yamada2015-01-05-2208/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* mpc8xx: remove NETVIA board supportMasahiro Yamada2015-01-05-1041/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Pantelis Antoniou <panto@intracom.gr>
* mpc8xx: remove R360MPI board supportMasahiro Yamada2015-01-05-1215/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* mpc8xx: remove RRvision board supportMasahiro Yamada2015-01-05-891/+0
| | | | | | | | | | | This board is still a non-generic board. Unused code in arch/powerpc/cpu/mpc8xx/video.c should be also deleted because CONFIG_VIDEO_ENCODER_AD7176, CONFIG_VIDEO_ENCODER_AD7177, CONFIG_VIDEO_ENCODER_AD7179 are not defined any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* mpc8xx: remove SPD823TS board supportMasahiro Yamada2015-01-05-555/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* mpc8xx: remove KUP4X, KUP4K board supportMasahiro Yamada2015-01-05-1756/+0
| | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Klaus Heydeck <heydeck@kieback-peter.de>
* mpc8xx: remove ELPT860 board supportMasahiro Yamada2015-01-05-1629/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: The LEOX team <team@leox.org>
* powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 supportMasahiro Yamada2015-01-05-1615/+0
| | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de>
* mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 supportMasahiro Yamada2015-01-05-151/+1
| | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-0/+41
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| * imx:mx6slevk add spi nor boot supportPeng Fan2014-12-31-0/+1
| | | | | | | | | | | | | | Add spi nor boot support for mx6slevk board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * imx:mx6sxsabresd add qspi supportPeng Fan2014-12-31-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the pad setting and enable qspi clock to support qspi flashes access. Add QSPI related macro in configuration header file. Note: mx6sxsabresd Revb board, 32M flash is used, but in header file, CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT initialization qspi_set_lut function uses 32BIT addr, however CONFIG_SPI_FLASH_BAR and 24BIT addr should be used to access bigger than 16MB size flash, and BRRD/BRWR should also be supported. Future patches will fix this. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-0/+115
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| * | ARM: tegra: Enable PCIe on Jetson TK1Thierry Reding2014-12-18-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes the second root port to a miniPCIe slot. Enable the PCIe controller and the network driver to allow the device to boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on CardhuThierry Reding2014-12-18-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC is available on the dock over the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable PCIe on TrimSliceThierry Reding2014-12-18-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Implement XUSB pad controllerThierry Reding2014-12-18-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-30-127/+652
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| * | mx6slevk: Remove get_board_rev()Fabio Estevam2014-12-30-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_board_rev() just returns the cpu revision, which does not make it really useful for distinguishing between revisions of the board. Let's get rid of get_board_rev() as it is not being used with its correct meaning. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm: mx6: novena: Add proper LVDS display supportMarek Vasut2014-12-30-23/+400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Repair the register configuration and add proper support for the display attached to both LVDS channels. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | arm: mx6: novena: Pull video handling into separate fileMarek Vasut2014-12-30-78/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull all of the video handling into a separate file, since a lot more code will be added and such code would polute the board file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | arm: mx6: novena: Pull GPIO definitions into headerMarek Vasut2014-12-30-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull the definitions of GPIOs into a separate header file, so that they can be used across all source files. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | arm: mx6: novena: Minor coding style fixMarek Vasut2014-12-30-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just zap multiple spaces and replace them with tabs properly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Sean Cross <xobs@kosagi.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2014-12-30-9/+112
| |\ \ | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | arm: mxs: olinuxino: move DRAM config tuning to SPLJan Luebbe2014-12-19-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The weak mxs_adjust_memory_params function is called from spl_mem_init.c, so it must be linked into the SPL to have an effect. Move it from mx23_olinuxino.c to spl_boot.c. This change was verified by reading back the register values. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * | | mx51evk: Fix MX51EVK_USB_CLK_EN_B definitionFabio Estevam2014-12-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | arm: mx6: gw_ventana: Change clock init to enable NAND related clocksStefan Roese2014-12-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise NAND booting is likely to fail. Since this disables the NAND related clocks and SPL can't load the main U-Boot from NAND. This problem was introduced with this patch: e25fbe3f (gw_ventana: Move the DCD settings to spl code) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | imx:mx6qarm2 add board level support for usbPeng Fan2014-12-19-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings and implement board_ehci_hcd_init Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | imx:mx6sabresd add board level support for usbPeng Fan2014-12-19-0/+68
| | |/ | |/| | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2014-12-30-16/+14
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| * | ARM: exynos5420: Leave VBUS GPIO configuration up to common codeSjoerd Simons2014-12-22-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 4a271cb1b4ffdf330 (exynos: usb: Switch USB VBUS GPIOs to be device tree configured) it's not needed for the board specific files to turn on the VBUS GPIO by hand as that gets done based on device tree. So drop the redundant code from the SMDK5420 board file. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos5420: fix compilation without parade videoSjoerd Simons2014-12-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all exynos 5420 based devices with an LCD also have a parade LVDS bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled and CONFIG_VIDEO_PARADE is not. As a side-effect move the parade functions from the exynos system header file to its own file. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang2014-12-22-0/+13
| |/ | | | | | | | | | | | | | | | | | | | | This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | ARM: rpi: consolidate board rev error checkingStephen Warren2014-12-29-7/+9
| | | | | | | | | | | | | | | | | | Create a fake model table entry with default values, so we can error check the board rev value once when querying it from the firmware, rather than error-checking for invalid board rev values every time the model table is used. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | ARM: rpi: support model A+Stephen Warren2014-12-29-2/+12
| | | | | | | | | | | | | | Add a board rev entry for the new model A+, and augment the board rev error handling code to be a bit more verbose. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | ARM: rpi: only set usbethaddr on relevant systemsStephen Warren2014-12-29-0/+17
| | | | | | | | | | | | | | | | | | Model A and CM RPis don't have an on-board USB Ethernet device. Hence, there's no point setting $usbethaddr based on the device fuses. Use the model detection code to gate this. Note that the fuses are actually programmed even on those devices though. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | vexpress64: take over maintenance of the semi vexpress64Linus Walleij2014-12-29-1/+1
| | | | | | | | | | | | | | | | | | As agreed with Steve Rae I'm taking over maintenance of the semihosted, emulated FVP/foundation model Versatile Express 64 bit board variant. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Steve Rae <srae@broadcom.com>
* | x86: crownbay: Enable Intel E1000 NIC supportBin Meng2014-12-18-0/+6
| | | | | | | | | | | | | | | | | | We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-18-0/+20
| | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+43
|/ | | | | | | | | | | Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-12-16-29/+33
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| * mpc85xx/t104xrdb: convert deep sleep to generic board interfaceTang Yuantian2014-12-15-29/+33
| | | | | | | | | | | | | | | | A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-0/+43
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| * | arm: socfpga: board: Repair Micrel PHY tuningPavel Machek2014-12-16-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add proper error checking into the PHY tuning patch. Make the PHY tunning only happen in case the KSZ9021 PHY is enabled in config. Call the config callback after the tuning finished. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@ti.com> Cc: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: set skew settings for ethernet phyDinh Nguyen2014-12-06-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
| * | arm: socfpga: Add myself as maintainer for the SoCrates boardStefan Roese2014-12-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Make ROM_SIZE configurable in KconfigBin Meng2014-12-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-39/+426
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