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* XPedite5200 board support cleanupPeter Tyser2008-12-29-3/+654
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-12/+12
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* XPedite5200 board supportPeter Tyser2008-12-19-5/+101
| | | | | | | Initial support for Extreme Engineering Solutions XPedite5200 - a MPC8548-based PMC single board computer. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 85xx: Enable inbound PCI config cycles for X-ES boardsPeter Tyser2008-12-19-0/+15
| | | | | | | Update X-ES Freescale boards to allow inbound PCI configuration cycles when configured as agent/endpoint. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* XPedite5370 board supportPeter Tyser2008-12-19-0/+1236
| | | | | | | | Initial support for Extreme Engineering Solutions XPedite5370 - a MPC8572-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* board/trab/memory.c: Fix compile problems.Wolfgang Denk2008-12-16-3/+3
| | | | | | | | | | | Apply changes from commit 44b4dbed to board/trab/memory.c, too. Actually we'd need a major cleanup here - as it turns out, board/trab/memory.c is more or less a verbatim copy of post/drivers/memory.c ... but then, trab is EOL anyway,r so this is not worth the effort. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/masterWolfgang Denk2008-12-16-4/+3
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| * Coding style cleanup, update CHANGELOG.Wolfgang Denk2008-12-16-1/+0
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Fix new found CFG_Jean-Christophe PLAGNIOL-VILLARD2008-12-14-3/+3
| | | | | | | | | | | | | | Also fix some minor typos. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* | trab: make trab_fkt standalone code independent of libgccWolfgang Denk2008-12-16-1/+8
|/ | | | | | Use our own local functions in lib_arm/ instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-12-13-10/+20
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| * ppc4xx: Disable EEPROM write access on PMC440 boardsMatthias Fuchs2008-12-10-1/+1
| | | | | | | | | | | | This patch disables EEPROM wrtie access by default on PMC440 board. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * ppc4xx: Fix Ethernet PHY LED configuration on PMC440 boardsMatthias Fuchs2008-12-10-4/+18
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * ppc4xx: Update TEXT_BASE for CPCI405 boardsMatthias Fuchs2008-12-10-5/+1
| | | | | | | | | | | | | | This patch fixes building U-Boot for CPCI405 boards. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2008-12-13-38/+38
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| * | sh: r2dplus fix register accessJean-Christophe PLAGNIOL-VILLARD2008-12-10-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: r2dplus/lowlevel_init: coding style fixJean-Christophe PLAGNIOL-VILLARD2008-12-10-21/+21
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: Migo-R: Update BSC valueNobuhiro Iwamatsu2008-12-10-16/+16
| |/ | | | | | | | | | | | | A value of BSC CS4 was wrong, Fixed it. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | microblaze: Remove XUPV2P boardMichal Simek2008-12-10-257/+0
|/ | | | | | | | | | | --- Microblaze platforms use generic settings and to have many platforms is confusing that's why I decided to remove this platform from U-BOOT. ml401 tree is sufficient for covering all Microblaze platforms. This change will go through microblaze custodian tree.
* evb64260: fix "cast to pointer from integer of different size" warningsWolfgang Denk2008-12-09-3/+7
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mgsuvd add the board-specific part of the HDLC driverGary Jennejohn2008-12-07-1/+280
| | | | Signed-off-by: Gary Jennejohn <garyj@denx.de>
* mgcoge add the board-specific part of the HDLC driverGary Jennejohn2008-12-07-1/+278
| | | | Signed-off-by: Gary Jennejohn <garyj@denx.de>
* keymile add the common parts of the HDLC driverGary Jennejohn2008-12-07-0/+749
| | | | | | | This implements the ICN protocol used across the backplane and is needed by all the keymile boards. Signed-off-by: Gary Jennejohn <garyj@denx.de>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-13/+24
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* lwmon, tqm8xx: Fix build errorsAnatolij Gustschin2008-12-06-4/+3
| | | | | | | | | | | | | | | | Commit 6b59e03e0237a40a2305ea385defdfd92000978b lcd: Let the board code show board-specific info introduced some bugs which prevent U-Boot building for lwmon board if CONFIG_LCD_INFO_BELOW_LOGO will be defined in the board configuration. Also "LCD enabled" building for TQM823L doesn't work since this commit. This patch fixes above-mentioned issues. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-3/+3
| | | | | | | | | Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: socrates: fix DDR SDRAM tlb entry configurationAnatolij Gustschin2008-12-03-0/+2
| | | | | | | | | | | | | | | | | | | | | since commit be0bd8234b9777ecd63c4c686f72af070d886517 tlb entry for socrates DDR SDRAM will be reconfigured by setup_ddr_tlbs() from initdram() causing an inconsistency with previously configured DDR SDRAM tlb entry from tlb_table: socrates>l2cam 7 9 IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS 7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX 8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX 9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX This patch makes the presence of the DDR SDRAM tlb entry in the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this inconsistency. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add CPU 2 errata workaround to all 8548 boardsPeter Tyser2008-12-03-19/+0
| | | | | | | | | | | All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM caseDave Liu2008-12-03-8/+4
| | | | | | | we need TLB entry for DDR at !SPD case. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: remove the unused ddr_enable_ecc in the board fileDave Liu2008-12-03-73/+0
| | | | | | | | | | The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-11-25-1351/+29
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| * ppc4xx: ml300 remove Xilinx BSP from ml300 folderMichal Simek2008-11-25-432/+0
| | | | | | | | | | | | | | | | This BSP should be outside u-boot source tree. The second reason is that xilinx ppc405 was moved to generic platform. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Use correct io accessors for PCI405Matthias Fuchs2008-11-25-35/+16
| | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Remove unused code from PCI405 codeMatthias Fuchs2008-11-25-871/+0
| | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: ML2 shouldn't include the 4xx EMAC driverStefan Roese2008-11-21-1/+0
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRsDave Mitchell2008-11-21-11/+12
| | | | | | | | | | | | | | | | | | | | | | Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-ubiWolfgang Denk2008-11-25-1/+2
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| * | ARM: Add Apollon UBI supportKyungmin Park2008-11-19-1/+2
| |/ | | | | | | | | | | | | | | To enable UBI on Apollon you need to uncomment the CONFIG_SYS_USE_UBI macro. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | AT91: Use AT91_CPU_CLOCK in displaysStelian Pop2008-11-21-4/+4
|/ | | | | | | | | | Introduce AT91_CPU_CLOCK and use it for displaying the CPU speed in the LCD driver. Also make AT91_MAIN_CLOCK and AT91_MASTER_CLOCK reflect the corresponding board clocks. Signed-off-by: Stelian Pop <stelian@popies.net>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-77/+244
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc86xxWolfgang Denk2008-11-18-48/+61
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| * mpc8641: fix address-cells default in old .dts detectionBecky Bruce2008-11-11-3/+3
| | | | | | | | | | | | | | | | address-cells defaults to 2, not 1; so in the unlikely event that it isn't specified, this patch is required for correct operation. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc8641: Try to detect old .dts filesBecky Bruce2008-11-10-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | Since we've changed the memory map of the board, be nice and add some checking to try to catch out-of-date .dts files. We do this by checking the CCSRBAR location in the .dts and comparing it to the CCSRBAR location in u-boot. If they don't match, a warning msg is printed. This isn't foolproof, but it's simple and will catch most of the cases where an out-of-date .dts is present, including all of the cases where a new u-boot is used with an old standard MPC8641 .dts file as supplied with Linux. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc8641: Support 36-bit physical addressingBecky Bruce2008-11-10-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates a memory map with all the devices in 36-bit physical space, in addition to the 32-bit map. The CCSR relocation is moved (again, sorry) to allow for the physical address to be 36 bits - this requires translation to be enabled. With 36-bit physical addressing enabled, we are no longer running with VA=PA translations. This means we have to distinguish between the two in the config file. The existing region name is used to indicate the virtual address, and a _PHYS variety is created to represent the physical address. Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc8641: Change 32-bit memory mapBecky Bruce2008-11-10-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash. The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware. In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file. Documentation has been changed to reflect the new map, as this change is user visible, and affects the OS which runs post-uboot. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc8641: Drop imaginary second flash bank, map 8MBBecky Bruce2008-11-10-1/+1
| | | | | | | | | | | | | | | | | | There's a lot of setup and foo for the second flash bank. The problem is, this board doesn't actually have one. Clean this up. Also, the flash is 8M in size. Get rid of the confusing aliased overmapping, and just map 8M. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * Merge commit 'wd/master'Jon Loeliger2008-11-10-5495/+843
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| * | 86xx: Make dram_size a phys_size_tBecky Bruce2008-11-03-6/+6
| | | | | | | | | | | | | | | | | | It's currently a long and should be phys_size_t. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * | mpc8641: Make PCI and RIO mutually exclusive, fix non-PCI buildBecky Bruce2008-11-03-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | You can't actually have both, and with some coming changes to change the memory map for the board and support 36-bit physical, we need the extra BAT that is being consumed by having both. I also make non-PCI configs build cleanly, for the sake of sanity. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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