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* Add a flattened device tree (fdt) command (2 of 2)Gerald Van Baren2007-03-31-6/+50
| | | | Modifications to the existing code to support the new fdt command.
* Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xxWolfgang Denk2007-03-29-0/+2
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| * Fix 8641HPCN problem with ld version 2.16Jon Loeliger2007-03-22-0/+2
| | | | | | | | | | | | | | | | (Dot outside sections problem). This fix is in the spirit of 807d5d7319330e336ab34a5623c5e0d73b87d540. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-blackfinWolfgang Denk2007-03-22-211/+4043
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| * \ Merge http://www.denx.de/git/u-bootAubrey Li2007-03-20-64/+29
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| * | | [Blackfin][PATCH] Add BF561 EZKIT board supportAubrey Li2007-03-20-0/+309
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| * | | Merge http://www.denx.de/git/u-bootAubrey Li2007-03-19-6/+15
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| * | | | [Blackfin][PATCH] minor cleanupAubrey Li2007-03-19-5/+5
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| * | | | [Blackfin][PATCH] Add BF537 stamp board supportAubrey Li2007-03-19-0/+3035
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| * | | | [Blackfin][PATCH] Fix BUILD_DIR option of MAKEALL building issueAubrey Li2007-03-12-14/+34
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| * | | | [Blackfin][PATCH] code cleanupAubrey Li2007-03-12-39/+42
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| * | | | [Blackfin][PATCH] code cleanupAubrey Li2007-03-10-6/+4
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| * | | | [Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform ↵Aubrey.Li2007-03-09-263/+730
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* | | | | Code cleanup. Update CHANGELOGWolfgang Denk2007-03-21-22/+10
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* | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-21-0/+2257
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| * | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-0/+2257
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| | * | | | [PATCH] Add AMCC Acadia (405EZ) eval board supportStefan Roese2007-03-21-0/+2257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC Acadia eval board. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | [PATCH] TQM8272: dont change the bits given from the HRCWHeiko Schocher2007-03-21-1/+1
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | for the SIUMCR and BCR Register. Fix the calculation for the EEprom Size Signed-off-by: Heiko Schocher <hs@denx.de>
* | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-16-58/+19
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| * | | | [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval boardStefan Roese2007-03-16-58/+19
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Make SC3 board build with 'make O='; use 'addcons' consistentlyWolfgang Denk2007-03-13-6/+10
|/ / / | | | | | | | | | | | | | | | (SC3 and Jupiter used to use 'addcon' instead). Signed-off-by: Wolfgang Denk wd@denx.de
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-6/+15
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| * | ppc4xx: Fix file mode of sequoia.cStefan Roese2007-03-08-0/+0
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Clear Sequoia/Rainier security engine reset bitsJohn Otken john@softadvances.com2007-03-08-0/+4
| | | | | | | | | | | | Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
| * | fixed ethernet phy configuration for plu405 boardMatthias Fuchs2007-03-08-6/+11
| | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-03-08-96/+1897
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| * | | mpc83xx: fix implicit declaration of function 'ft_get_prop' warningsKim Phillips2007-03-02-0/+6
| | | | | | | | | | | | | | | | (cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
| * | | mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffersKim Phillips2007-03-02-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable G1TXCLK, G2TXCLK h/w buffers. This patch fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com>
| * | | mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xxXie Xiaobo2007-03-02-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * | | mpc83xx: Add support for the MPC8349E-mITX-GPTimur Tabi2007-03-02-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: Delete sdram_init() for MPC8349E-mITXTimur Tabi2007-03-02-87/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no SDRAM on any of the 8349 ITX variants, so function sdram_init() never does anything. This patch deletes it. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: U-Boot support for Wind River SBC8349Paul Gortmaker2007-03-02-0/+1134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul.
| * | | mpc83xx: Remove a redundant semicolon in mpc8349itx.cSam Song2007-03-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A redundant semicolon existed in mpc8349itx.c should be removed. Signed-off-by: Sam Song <samsongshu@yahoo.com.cn>
| * | | mpc83xx: Add support for the MPC832XEMDS boardDave Liu2007-03-02-0/+690
| | | | | | | | | | | | | | | | | | | | | | | | This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | | mpc83xx: streamline the 83xx immr head fileDave Liu2007-03-02-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
* | | Merge with /home/hs/jupiter/u-bootWolfgang Denk2007-03-08-0/+534
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| * | [PATCH] Added support for the jupiter board.Heiko Schocher2007-02-16-0/+534
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-597/+94
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| * \ \ Merge with /home/stefan/git/u-boot/yucca-ddr2Stefan Roese2007-03-08-597/+94
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| | * | | [PATCH] Update AMCC Luan 440SP eval board supportStefan Roese2007-03-08-226/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | [PATCH] Update AMCC Yucca 440SPe eval board supportStefan Roese2007-03-08-371/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Small AMCC Katmai 440SPe updateStefan Roese2007-03-08-0/+10
| | | |/ | | |/| | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-07-63/+19
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| * | | [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval boardStefan Roese2007-03-07-63/+19
| |/ / | | | | | | | | | | | | | | | | | | | | | Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
* | | UC101: fix compiler warningsWolfgang Denk2007-03-07-9/+9
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* | | HMI1001: fix build error, cleanup compiler warnings.Wolfgang Denk2007-03-07-9/+9
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* | | [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese2007-03-06-8/+13
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx-merge-srStefan Roese2007-03-01-5/+7
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| * | MCC200: Fixes for update procedureSergei Poselenov2007-02-28-5/+7
| | | | | | | | | | | | | | | | | | - fix logic error in image type handling - make sure file system images (cramfs etc.) get stored in flash with image header stripped so they can be mounted through MTD
* | | Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-03-01-24/+110
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