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* ENGR00255977 mx6sl: correct the information for chip and board revisionRobby Cai2013-04-16-9/+18
| | | | | | | | | | mx6sl chip revision is from different-offset register in anatop module comparing to other mx6 series. This patch fixes it and also uses board 'RevC' to indicate the latest board revision if this information can not be obtained from fuse. Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit 39e36b5e5a7cfe53fd6e286d9fe9024b365f1a29)
* ENGR00254470-4 mx6q-hdmidongle:sata device can't work properly on most boardsRichard Zhu2013-04-16-16/+0
| | | | | | | | | | | | | | | | Revert "ENGR00241595-4 mx6q-hdmidongle:Enable SATA PHY PDDQ default" This reverts commit d33eefe083563a082840a46ec9cac21f98fad550. Reasons: * according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is powered down automatically according to SATA controller power mode SATA port support Disable/Slumber/Partial/Enabled(OOB) The SATA PHY PDDQ mode is one-shot and recommeded to be used for test, SATA would not work properly if the PHY PDDQ mode is enabled in U-boot. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00254470-3 mx6q-sabreauto:sata device can't work properly on most boardsRichard Zhu2013-04-16-21/+0
| | | | | | | | | | | | | | | | Revert "ENGR00241595-3 mx6q-sabreauto:Enable SATA PHY PDDQ default" This reverts commit 027af67a25773a0872659788eab0c09b72e2bbe0. Reasons: * according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is powered down automatically according to SATA controller power mode SATA port support Disable/Slumber/Partial/Enabled(OOB) The SATA PHY PDDQ mode is one-shot and recommeded to be used for test, SATA would not work properly if the PHY PDDQ mode is enabled in U-boot. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00254470-2 mx6q-arm2:sata device can't work properly on most boardsRichard Zhu2013-04-16-21/+0
| | | | | | | | | | | | | | | | Revert "ENGR00241595-2 mx6q-arm2:Enable SATA PHY PDDQ default" This reverts commit b10e0c4559602adacb22670506a1956a50cfd247. Reasons: * according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is powered down automatically according to SATA controller power mode SATA port support Disable/Slumber/Partial/Enabled(OOB) The SATA PHY PDDQ mode is one-shot and recommeded to be used for test, SATA would not work properly if the PHY PDDQ mode is enabled in U-boot. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00254470-1 mx6q-sd:sata device can't work properly on most boardsRichard Zhu2013-04-16-22/+0
| | | | | | | | | | | | | | | | Revert "ENGR00241595-1 mx6q-sabresd:Enable SATA PHY PDDQ default" This reverts commit 9cb937432d1dc8d2c31afa5194f1ef0d8bdc0392. Reasons: * according to SATA Power mode (in SATA protocol) PHY TX/RX/CLK is powered down automatically according to SATA controller power mode SATA port support Disable/Slumber/Partial/Enabled(OOB) The SATA PHY PDDQ mode is one-shot and recommeded to be used for test, SATA would not work properly if the PHY PDDQ mode is enabled in U-boot. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00244769-3 [NOR FLASH]-Improve WEIM NOR speedOliver Brown2013-02-13-3/+3
| | | | | | | | Improvements for WEIM NOR read performance. Changed burst and page size to 8 words. Changed read wait states to 10 and page read wait states to 4. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00243038: make get_mmc_env_devno to be a generic functionJason Liu2013-02-04-95/+3
| | | | | | | | | | | | | Currently, each board has one same function called get_mmc_env_devno, this will make the code a little bit duplication. We can make the get_mmc_env_devno to be a generic function, thus we can remove all the scattered function definition in each board file. And the patch also remove the boot check. Firstly, this check is needless, secondly, this will break the second boot support,for example: first boot from SPI, then switch to SD/MMC boot. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00242042 MX6DQ/DL: fix boot fail issue on mx6dl boardsjb4.2.1_1.0.0-alphaLin Fuzhen2013-01-28-9/+33
| | | | | | | | MX6DQ and MX6DL share the common board file, but only MX6DQ has built-in SATA, for the SATA PDDQ should be enabled default, so it needs to add code to distinguish different chip ID. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00241595-4 mx6q-hdmidongle:Enable SATA PHY PDDQ defaultLin Fuzhen2013-01-25-20/+29
| | | | | | | | | | | | | | | | The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA defined or not in board config file. If SATA feature is not config, then the PDDQ will not be set, SATA PHY will not entry in Low Power Mode, and it will consume some power even there is no sata devices on board. This patch: 1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in board config file, SATA module will disable PDDQ first when used phy, so default enable PDDQ will not affect SATA feature. 2 It needs a delay to wait for SATA PHY initialize after enable it, otherwise write the phy registers will fail. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00241595-3 mx6q-sabreauto:Enable SATA PHY PDDQ defaultLin Fuzhen2013-01-25-16/+18
| | | | | | | | | | | | | | | | The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA defined or not in board config file. If SATA feature is not config, then the PDDQ will not be set, SATA PHY will not entry in Low Power Mode, and it will consume some power even there is no sata devices on board. This patch: 1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in board config file, SATA module will disable PDDQ first when used phy, so default enable PDDQ will not affect SATA feature. 2 It needs a delay to wait for SATA PHY initialize after enable it, otherwise write the phy registers will fail. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00241595-2 mx6q-arm2:Enable SATA PHY PDDQ defaultLin Fuzhen2013-01-25-18/+18
| | | | | | | | | | | | | | | | The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA defined or not in board config file. If SATA feature is not config, then the PDDQ will not be set, SATA PHY will not entry in Low Power Mode, and it will consume some power even there is no sata devices on board. This patch: 1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in board config file, SATA module will disable PDDQ first when used phy, so default enable PDDQ will not affect SATA feature. 2 It needs a delay to wait for SATA PHY initialize after enable it, otherwise write the phy registers will fail. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00241595-1 mx6q-sabresd:Enable SATA PHY PDDQ defaultLin Fuzhen2013-01-25-29/+32
| | | | | | | | | | | | | | | | The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA defined or not in board config file. If SATA feature is not config, then the PDDQ will not be set, SATA PHY will not entry in Low Power Mode, and it will consume some power even there is no sata devices on board. This patch: 1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in board config file, SATA module will disable PDDQ first when used phy, so default enable PDDQ will not affect SATA feature. 2 It needs a delay to wait for SATA PHY initialize after enable it, otherwise write the phy registers will fail. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00230437: mx6: epdc: EPDC I/O setup after V3p3 is enableFugang Duan2013-01-08-243/+380
| | | | | | | | | | EPDC will be used when splash screen is shown, EPDC io setup is done before 3V3 digitial power, which cause critical chip burn-out for all platforms. To follow the E-Ink specification, setup EPDC I/O after V3p3 is enable. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00235540 add sabreauto_6q config for androidb022472012-12-18-0/+51
| | | | | | Support fastboot and recovery Signed-off-by: b02247 <b02247@freescale.com>
* ENGR00236472 Update DDR script of ARD solo emulationAlejandro Sierra2012-12-13-77/+56
| | | | | | | | Update DDR script of ARD solo emulation, the ddr script based on the following commit from ddr-scripts-rel git: dfde48e Added MX6Solo ARD DDR3 init. Signed-off-by: Alejandro Sierra <b18039@freescale.com>
* ENGR00236902: mx6solo_sabresd: update the DDR script for solo-sabresdJason Liu2012-12-13-107/+71
| | | | | | | | | This patch update the DDR script for mx6solo_sabresd board. The DDR script based on the following commit from ddr-scripts-rel.git 9d4e11a Added MX6Solo SabreSD DDR3 script Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00236620: Add Android fastboot and recovery reboot supportNitin Garg2012-12-11-82/+10
| | | | | | | Add support for Android fastboot and recovery reboot commands for iMX5. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR000234991 MX6DL/ARD: Two boards met kernel dump during boot upjb4.1.2_1.0.0-betaJason Liu2012-12-05-8/+8
| | | | | | | | | | | | The issue is caused by DDR script changed io pads to DDR differential mode but forget to do the calibration data update. This patch updated the DDR script on MX6DL ARD board based on the commit on the ddr-scripts-rel: 53121e0 Updated MX6DL and MX6DQ ARD and SabreSD scripts with new calibration values for IO pads set to differential mode; Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00235564: i.mx6 u-boot: change plugin to use ROM API table for code jumpEric Sun2012-12-03-12/+21
| | | | | | | | | | | | | | The original plugin code uses hard coded assembly address for the code jump to "pu_irom_hwcnfg_setup", it can only works for specific chip version, for a new TO, the assembly address will change, and the plugin code simply fails. In fact there is an API entry table in a fixed ROM location, it contains the entry to the "pu_irom_hwcnfg_setup". This patch retrieve the jump address from this API table, thus avoid the limitation for current implementation. Apply to all plugin enabled platforms, MX6Q/DL ARM2, MX6SL ARM2/EVK Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00223037 fsl: Add new board HDMI dongle for imx6 Q/DL.Zhang Xiaodong2012-11-28-0/+2054
| | | | | | Add HDMIdongle board for imx6Q/DL under board/freescale. Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
* ENGR00233168 - U-Boot fails to boot from eMMCOliver Brown2012-11-27-196/+80
| | | | | | Aligning the flash header to remove the boot plugin as in previous release. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00233928 i.mx6q/sabresd: update the DDR script for i.MX6Q sabresd boardJason Liu2012-11-26-108/+102
| | | | | | | | This commit update the DDR script for i.MX6Q sabresd board based on the top of the following commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00234353-3: mx6q_sabreauto remove EIM_A24 nor padsAdrian Alonso2012-11-20-2/+0
| | | | | | | | | | * Remove EIM_A24 nor pads as this are used for io steer control and are not connectted to NOR flash memory. * Fix conflict access when it's used as io control gpio. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00233366-5 Anatop PFUZE: move LDO bypass code to kernelRobin Gong2012-11-19-121/+0
| | | | | | | move LDO bypass code and one PFUZE1.0 workaround code to kernel. Remove CONFIG_MX6_INTER_LDO_BYPASS in u-boot Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00233933 i.mx6dl/sabresd: update the DDR script for i.MX6DL sabresd boardJason Liu2012-11-16-96/+90
| | | | | | | | This patch update the DDR script for the i.MX6DL sabresd board The script is based on top the commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00233709-2 i.mx6q/sabreauto: update the DDR script for i.mx6q AI board:Jason Liu2012-11-16-110/+105
| | | | | | | | | This commit update the DDR script for i.MX6Q Sabreauto(AI) board. The script is based on top the commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00233709-1 i.mx6dl/sabreauto: update the DDR script for i.mx6dl AI board:Jason Liu2012-11-16-18/+17
| | | | | | | | | This commit update the DDR script for i.MX6DL Sabreauto(AI) board. The script is based on top the commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00233881 Camera mx6q_sabresd:swap VGEN5&VGEN3 to fix camera streaks issueRobin Gong2012-11-16-0/+27
| | | | | | | | | On mx6q_sabresd RevC board, there is camera streaks issue, after HW check, they think there is current limit risk because VDDHIGH_IN and camera 2.8V power share the same VGEN5, they suggest seprate them, so we use VGEN5 as VDDHIGH_IN and use VGEN3 as camera 2.8V power supply. Also increase VDDHIG_IN from 2.8V to 3.0V to align with latest datasheet Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00233716-2: mx6q_sabreauto flash u-boot into spi-nor fails to bootAdrian Alonso2012-11-15-28/+24
| | | | | | | | | | * Fix spi-nor boot failure * Fix unconfigured gpio pad setting when spi-nor or weim-nor on steer control gpios * Group gpio access only when I2C is enabled and restore route paths to avoid conflicts on shared pads Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00233730 PFUZE mx6q_sabresd: remove extra increase for PFUZE toleranceRobin Gong2012-11-15-14/+0
| | | | | | | There is no more tolerance issue on PFUZE, it will be only 25mV, so that we no need increase VDDSOC_IN from 1.375V to 1.425V. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00233307 Need secure/encrypted boot for Widevine support.Dan Douglass2012-11-12-0/+33
| | | | | | | | | | | | | | | | | | | | * Adding the config option CONFIG_SECURE_BOOT to the SabreSD board, but defaulting it to be disabled. Removed the CONFIG_SECURE_BOOT key from mx6q_arm2_android.h so that it is only in one file, include/configs/mx6q_arm2.h * Fixed up an address alignment check in authenticate_image(). The test would fail in the event the address is already aligned. Also, added some debug code which can be enabled to assist in testing secure images. * Added support for authenticating an image when using booti. * Adding support for secure boot to the Sabre SD board. * Added support for encrypted boot to mx6q arm2 board linker script. Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
* ENGR00232682 mx6sl snvs: fix long press ONOFF failed issue in u-bootLin Fuzhen2012-11-09-0/+27
| | | | | | | | | the same as TKT104835 reported on MX6Q/DL Need set Power Supply Glitch to 0x41736166 and clear Power Supply Glitch Detect bit when POR or reboot or power on, otherwise system could not be power off anymore, it will power up auto agian. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00230364 - imx6sl: FEC: fix cycle reboot fail in EVK platform for bootp.Fugang Duan2012-11-08-2/+9
| | | | | | | | | | | In some imx6sl evk boards, fec cannot work fine while doing cycle reboot via to execute command "reboot" in kernel. The root cause: phys clock source is closed when reboot system, and LAN8720 status machine is in disorder. So it needs to do phy hardware reset to make phy enter normal state machine. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00231781 fsl common:Align reversed color logo to standardLiu Ying2012-10-31-612/+612
| | | | | | | | | This patch removes the 'semiconductor' word in the freescale reversed color logo to align with the standard(preferred) one which can be found at the link: http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-logosdisclaim Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00230967 Enable recovery mode by keys when bootLiGang2012-10-30-18/+68
| | | | | | | | | | 1. Add matrix key support 2. Add recovery mode support by pressing power key and volume down key when boot SW10 on MX6SL-EVK board configed as volume down key. SW1 on MX6SL-EVK board configed as power key Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00230981-1 pfuze:set all switches to PFM mode in standbyRobin Gong2012-10-26-78/+75
| | | | | | | | | | | To save power, set all switches to PFM mode in standby,although PFM mode need 6% tolerance.But it will be implemented in kernel, and move the workaround which all buck switches need be configured PWM mode on PF100 1.0 Another two change is: 1. u-boot will print PFUZE device id and revision id. 2. add value check for i2c write and read. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00230391: Fix build fail issue of sataTerry Lv2012-10-19-3/+5
| | | | | | | | | | | | | | | | | | | | | Fix build fail issue of sata. mx6q_arm2.c: In function 'sata_initialize': mx6q_arm2.c:261:6: error: 'sata_curr_device' undeclared (first use in this function) mx6q_arm2.c:261:6: note: each undeclared identifier is reported only once for each function it appears in mx6q_arm2.c:299:2: warning: implicit declaration of function '__sata_initialize' [-Wimplicit-function-declaration] mx6q_arm2.c: In function 'setup_sata': mx6q_arm2.c:346:6: error: 'sata_curr_device' undeclared (first use in this function) mx6q_arm2.c: At top level: mx6q_arm2.c:81:12: warning: 'system_rev' defined but not used [-Wunused-variable] make[1]: *** [mx6q_arm2.o] Error 1 Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00230334: Fix the mx53_smd_android configNitin Garg2012-10-18-6/+5
| | | | | | | | Update the u-boot config for mx53 smd android to include the correct boot env, enable boot splash, increase the cmdline buffer, tokens and 1G DDR. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00229789 AHCI Disable SATA PHY in initializationRichard Zhu2012-10-17-0/+199
| | | | | | | | * disable SATA PHY in default * add sata_initialize() func used to re-initialize SATA when sata is used. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00229456 Support for 64bit DDR configuration for ARDAlejandro Sierra2012-10-12-0/+117
| | | | | | | Added support for 64bit DDR configuration on DL chip. On ARD platform Signed-off-by: Alejandro Sierra <b18039@freescale.com>
* ENGR00228238 i.mx6/i.mx6dl: sabresd: add solo-ddr32bit supportJason Liu2012-10-11-2/+125
| | | | | | | | This patch adds the solo-ddr32bit config support. The DDR script got from: http://compass.freescale.net/livelink/livelink/227589697/ MX6DL_init_DDR3_400MHz_32bit_For_SD_1.0.inc.txt?func=doc.Fetch&nodeid=227589697 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00223797-1 MX6 SabreSD:Align IPU related clocks with kernelLiu Ying2012-09-27-18/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aligns IPU related clocks with imx_3.0.35(_android) kernel setting to support smooth transition from uboot splash screen to kernel stage. The IPU related clock trees are: 1) MX6DQ SabreSD: ipu1_clk -- osc_clk(24M)->pll2_528_bus_main_clk(528M)->periph_clk(528M) ->mmdc_ch0_axi_clk(528M)->ipu1_clk(264M) ipu1_pixel_clk_x -- osc_clk(24M)->pll2_528_bus_main_clk(528M)-> pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)-> ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M) 2) MX6DL SabreSD: ipu1_clk -- osc_clk(24M)->pll3_usb_otg_main_clk(480M)-> pll3_pfd_540M(540M)->ipu1_clk(270M) ipu1_pixel_clk_x -- osc_clk(24M)->pll2_528_bus_main_clk(528M)-> pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)-> ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M) Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00223794 MX6 SabreSD:Enable LVDS panel pwm backlightLiu Ying2012-09-27-14/+13
| | | | | | | | | | | | | This patch enables pwm backlight for LVDS panel and stops using gpio backlight to align with kernel to avoid unstable backlight when booting into kernel, as kernel usually uses pwm backlight instead of gpio backlight. Following items are done to support this: 1) Add PWM1 and PWM2 controller base addresses. 2) Change PIN SD1_DAT3 mux from GPIO to PWM1_PWMO. 3) Set default backlight density to 50%. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00222170: Add mx6sl_evk_android_config for mx6sl evk boardLiGang2012-09-06-1/+18
| | | | | | | - mx6sl_evk_android.h is a new file, copied from mx6sl_arm2_android.h - set default sdio port as mmc1 Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00219316-2: mx6q sabreauto enable lvds backlight by defaultAdrian Alonso2012-08-29-25/+32
| | | | | | | | | | | | | * Enable lvds backlight by default, configure io_expander A to enable backlight. * As weimnor_d18, spinor_d18, i2c3_sda share the pad MX6Q_PAD_EIM_D18 if wiemnor or spinor is enabled it overrides i2c3 settings and kernel fails to configure io_expander causing read/write errors. * This commit allows a default configuration on control lines behind io_expander A. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00221013 MX6 SabreSD:Disable LVDS panel CABC functionLiu Ying2012-08-28-0/+38
| | | | | | | | | This patch sets CABC_EN0/1 pins to low to disable LVDS panel CABC function. This function will turn backlight automatically according to display content which may cause potential unstable backlight phenomena. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00221135: imx6x: clear PowerDown Enable bit of WDOG1_WMCRRobby Cai2012-08-24-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC spec: --- The Power down Counter inside WDOG-1 will be enabled out of reset. This counter has a fixed time-out value of 16 seconds, after which it will drive the WDOG-1 signal low. To prevent this, the software must disable this counter by clearing the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR) within 16 seconds of reset de-assertion. Once disabled, this counter cannot be enabled again until the next system reset occurs. This feature is provided to prevent the hanging up of cores after reset, as WDOG-1 is not enabled out of reset. --- NOTE for the last sentence: This feature requires a dedicated WDOG_B pin for it. The fact that changing the IOMUX configuration can alter the WDOG_B functionality (GPIO by default) is not ideal as it defeats the purpose of this feature. But it still takes effect when the muxed pin is configured as WDOG_B within 16 seconds. Clear PDE bit to avoid WDOG_B (aka, WDOG-1) assertion. Tested on MX6SL. May add this for other MX6x. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00220824: mx6sl_evk: mmc: only SD1 supports 8bit on evk board.Ryan QIAN2012-08-21-4/+0
| | | | | | - configure SD1 to support 8bit on evk Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217505-8 uboot: MX6Q-ARD: set the default gpmi clock to 20MHzHuang Shijie2012-08-20-3/+2
| | | | | | Set the default clock to 20MHz. The 11Mhz is too slow. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00220486 Modify ODT values for Solo AIAlejandro Sierra2012-08-20-4/+4
| | | | | | | | | | | | | | | | | | Modify ODT values for Solo AI. Some Solo boards did not passed the "mtest" from uboot using the previous configuration. Old configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) New configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) Signed-off-by: Alejandro Sierra <b18039@freescale.com>
generated by cgit v1.1 at 2024-12-26 09:54:28 +0000