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* ENGR000234991 MX6DL/ARD: Two boards met kernel dump during boot upjb4.1.2_1.0.0-betaJason Liu2012-12-05-8/+8
| | | | | | | | | | | | The issue is caused by DDR script changed io pads to DDR differential mode but forget to do the calibration data update. This patch updated the DDR script on MX6DL ARD board based on the commit on the ddr-scripts-rel: 53121e0 Updated MX6DL and MX6DQ ARD and SabreSD scripts with new calibration values for IO pads set to differential mode; Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00235564: i.mx6 u-boot: change plugin to use ROM API table for code jumpEric Sun2012-12-03-12/+21
| | | | | | | | | | | | | | The original plugin code uses hard coded assembly address for the code jump to "pu_irom_hwcnfg_setup", it can only works for specific chip version, for a new TO, the assembly address will change, and the plugin code simply fails. In fact there is an API entry table in a fixed ROM location, it contains the entry to the "pu_irom_hwcnfg_setup". This patch retrieve the jump address from this API table, thus avoid the limitation for current implementation. Apply to all plugin enabled platforms, MX6Q/DL ARM2, MX6SL ARM2/EVK Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00223037 fsl: Add new board HDMI dongle for imx6 Q/DL.Zhang Xiaodong2012-11-28-0/+2054
| | | | | | Add HDMIdongle board for imx6Q/DL under board/freescale. Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
* ENGR00233168 - U-Boot fails to boot from eMMCOliver Brown2012-11-27-196/+80
| | | | | | Aligning the flash header to remove the boot plugin as in previous release. Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
* ENGR00233928 i.mx6q/sabresd: update the DDR script for i.MX6Q sabresd boardJason Liu2012-11-26-108/+102
| | | | | | | | This commit update the DDR script for i.MX6Q sabresd board based on the top of the following commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00234353-3: mx6q_sabreauto remove EIM_A24 nor padsAdrian Alonso2012-11-20-2/+0
| | | | | | | | | | * Remove EIM_A24 nor pads as this are used for io steer control and are not connectted to NOR flash memory. * Fix conflict access when it's used as io control gpio. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00233366-5 Anatop PFUZE: move LDO bypass code to kernelRobin Gong2012-11-19-121/+0
| | | | | | | move LDO bypass code and one PFUZE1.0 workaround code to kernel. Remove CONFIG_MX6_INTER_LDO_BYPASS in u-boot Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00233933 i.mx6dl/sabresd: update the DDR script for i.MX6DL sabresd boardJason Liu2012-11-16-96/+90
| | | | | | | | This patch update the DDR script for the i.MX6DL sabresd board The script is based on top the commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00233709-2 i.mx6q/sabreauto: update the DDR script for i.mx6q AI board:Jason Liu2012-11-16-110/+105
| | | | | | | | | This commit update the DDR script for i.MX6Q Sabreauto(AI) board. The script is based on top the commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00233709-1 i.mx6dl/sabreauto: update the DDR script for i.mx6dl AI board:Jason Liu2012-11-16-18/+17
| | | | | | | | | This commit update the DDR script for i.MX6DL Sabreauto(AI) board. The script is based on top the commit on ddr-scripts-rel: 02b8a73 removed some verbage (comments) from init, no changes to actual init Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00233881 Camera mx6q_sabresd:swap VGEN5&VGEN3 to fix camera streaks issueRobin Gong2012-11-16-0/+27
| | | | | | | | | On mx6q_sabresd RevC board, there is camera streaks issue, after HW check, they think there is current limit risk because VDDHIGH_IN and camera 2.8V power share the same VGEN5, they suggest seprate them, so we use VGEN5 as VDDHIGH_IN and use VGEN3 as camera 2.8V power supply. Also increase VDDHIG_IN from 2.8V to 3.0V to align with latest datasheet Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00233716-2: mx6q_sabreauto flash u-boot into spi-nor fails to bootAdrian Alonso2012-11-15-28/+24
| | | | | | | | | | * Fix spi-nor boot failure * Fix unconfigured gpio pad setting when spi-nor or weim-nor on steer control gpios * Group gpio access only when I2C is enabled and restore route paths to avoid conflicts on shared pads Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00233730 PFUZE mx6q_sabresd: remove extra increase for PFUZE toleranceRobin Gong2012-11-15-14/+0
| | | | | | | There is no more tolerance issue on PFUZE, it will be only 25mV, so that we no need increase VDDSOC_IN from 1.375V to 1.425V. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00233307 Need secure/encrypted boot for Widevine support.Dan Douglass2012-11-12-0/+33
| | | | | | | | | | | | | | | | | | | | * Adding the config option CONFIG_SECURE_BOOT to the SabreSD board, but defaulting it to be disabled. Removed the CONFIG_SECURE_BOOT key from mx6q_arm2_android.h so that it is only in one file, include/configs/mx6q_arm2.h * Fixed up an address alignment check in authenticate_image(). The test would fail in the event the address is already aligned. Also, added some debug code which can be enabled to assist in testing secure images. * Added support for authenticating an image when using booti. * Adding support for secure boot to the Sabre SD board. * Added support for encrypted boot to mx6q arm2 board linker script. Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
* ENGR00232682 mx6sl snvs: fix long press ONOFF failed issue in u-bootLin Fuzhen2012-11-09-0/+27
| | | | | | | | | the same as TKT104835 reported on MX6Q/DL Need set Power Supply Glitch to 0x41736166 and clear Power Supply Glitch Detect bit when POR or reboot or power on, otherwise system could not be power off anymore, it will power up auto agian. Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
* ENGR00230364 - imx6sl: FEC: fix cycle reboot fail in EVK platform for bootp.Fugang Duan2012-11-08-2/+9
| | | | | | | | | | | In some imx6sl evk boards, fec cannot work fine while doing cycle reboot via to execute command "reboot" in kernel. The root cause: phys clock source is closed when reboot system, and LAN8720 status machine is in disorder. So it needs to do phy hardware reset to make phy enter normal state machine. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00231781 fsl common:Align reversed color logo to standardLiu Ying2012-10-31-612/+612
| | | | | | | | | This patch removes the 'semiconductor' word in the freescale reversed color logo to align with the standard(preferred) one which can be found at the link: http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-logosdisclaim Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00230967 Enable recovery mode by keys when bootLiGang2012-10-30-18/+68
| | | | | | | | | | 1. Add matrix key support 2. Add recovery mode support by pressing power key and volume down key when boot SW10 on MX6SL-EVK board configed as volume down key. SW1 on MX6SL-EVK board configed as power key Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00230981-1 pfuze:set all switches to PFM mode in standbyRobin Gong2012-10-26-78/+75
| | | | | | | | | | | To save power, set all switches to PFM mode in standby,although PFM mode need 6% tolerance.But it will be implemented in kernel, and move the workaround which all buck switches need be configured PWM mode on PF100 1.0 Another two change is: 1. u-boot will print PFUZE device id and revision id. 2. add value check for i2c write and read. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00230391: Fix build fail issue of sataTerry Lv2012-10-19-3/+5
| | | | | | | | | | | | | | | | | | | | | Fix build fail issue of sata. mx6q_arm2.c: In function 'sata_initialize': mx6q_arm2.c:261:6: error: 'sata_curr_device' undeclared (first use in this function) mx6q_arm2.c:261:6: note: each undeclared identifier is reported only once for each function it appears in mx6q_arm2.c:299:2: warning: implicit declaration of function '__sata_initialize' [-Wimplicit-function-declaration] mx6q_arm2.c: In function 'setup_sata': mx6q_arm2.c:346:6: error: 'sata_curr_device' undeclared (first use in this function) mx6q_arm2.c: At top level: mx6q_arm2.c:81:12: warning: 'system_rev' defined but not used [-Wunused-variable] make[1]: *** [mx6q_arm2.o] Error 1 Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00230334: Fix the mx53_smd_android configNitin Garg2012-10-18-6/+5
| | | | | | | | Update the u-boot config for mx53 smd android to include the correct boot env, enable boot splash, increase the cmdline buffer, tokens and 1G DDR. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00229789 AHCI Disable SATA PHY in initializationRichard Zhu2012-10-17-0/+199
| | | | | | | | * disable SATA PHY in default * add sata_initialize() func used to re-initialize SATA when sata is used. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00229456 Support for 64bit DDR configuration for ARDAlejandro Sierra2012-10-12-0/+117
| | | | | | | Added support for 64bit DDR configuration on DL chip. On ARD platform Signed-off-by: Alejandro Sierra <b18039@freescale.com>
* ENGR00228238 i.mx6/i.mx6dl: sabresd: add solo-ddr32bit supportJason Liu2012-10-11-2/+125
| | | | | | | | This patch adds the solo-ddr32bit config support. The DDR script got from: http://compass.freescale.net/livelink/livelink/227589697/ MX6DL_init_DDR3_400MHz_32bit_For_SD_1.0.inc.txt?func=doc.Fetch&nodeid=227589697 Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00223797-1 MX6 SabreSD:Align IPU related clocks with kernelLiu Ying2012-09-27-18/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aligns IPU related clocks with imx_3.0.35(_android) kernel setting to support smooth transition from uboot splash screen to kernel stage. The IPU related clock trees are: 1) MX6DQ SabreSD: ipu1_clk -- osc_clk(24M)->pll2_528_bus_main_clk(528M)->periph_clk(528M) ->mmdc_ch0_axi_clk(528M)->ipu1_clk(264M) ipu1_pixel_clk_x -- osc_clk(24M)->pll2_528_bus_main_clk(528M)-> pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)-> ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M) 2) MX6DL SabreSD: ipu1_clk -- osc_clk(24M)->pll3_usb_otg_main_clk(480M)-> pll3_pfd_540M(540M)->ipu1_clk(270M) ipu1_pixel_clk_x -- osc_clk(24M)->pll2_528_bus_main_clk(528M)-> pll2_pfd_352M(452.57M)->ldb_dix_clk(64.65M)-> ipu1_di_clk_x(64.65M)->ipu1_pixel_clk_x(64.65M) Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00223794 MX6 SabreSD:Enable LVDS panel pwm backlightLiu Ying2012-09-27-14/+13
| | | | | | | | | | | | | This patch enables pwm backlight for LVDS panel and stops using gpio backlight to align with kernel to avoid unstable backlight when booting into kernel, as kernel usually uses pwm backlight instead of gpio backlight. Following items are done to support this: 1) Add PWM1 and PWM2 controller base addresses. 2) Change PIN SD1_DAT3 mux from GPIO to PWM1_PWMO. 3) Set default backlight density to 50%. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00222170: Add mx6sl_evk_android_config for mx6sl evk boardLiGang2012-09-06-1/+18
| | | | | | | - mx6sl_evk_android.h is a new file, copied from mx6sl_arm2_android.h - set default sdio port as mmc1 Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00219316-2: mx6q sabreauto enable lvds backlight by defaultAdrian Alonso2012-08-29-25/+32
| | | | | | | | | | | | | * Enable lvds backlight by default, configure io_expander A to enable backlight. * As weimnor_d18, spinor_d18, i2c3_sda share the pad MX6Q_PAD_EIM_D18 if wiemnor or spinor is enabled it overrides i2c3 settings and kernel fails to configure io_expander causing read/write errors. * This commit allows a default configuration on control lines behind io_expander A. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00221013 MX6 SabreSD:Disable LVDS panel CABC functionLiu Ying2012-08-28-0/+38
| | | | | | | | | This patch sets CABC_EN0/1 pins to low to disable LVDS panel CABC function. This function will turn backlight automatically according to display content which may cause potential unstable backlight phenomena. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00221135: imx6x: clear PowerDown Enable bit of WDOG1_WMCRRobby Cai2012-08-24-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC spec: --- The Power down Counter inside WDOG-1 will be enabled out of reset. This counter has a fixed time-out value of 16 seconds, after which it will drive the WDOG-1 signal low. To prevent this, the software must disable this counter by clearing the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR) within 16 seconds of reset de-assertion. Once disabled, this counter cannot be enabled again until the next system reset occurs. This feature is provided to prevent the hanging up of cores after reset, as WDOG-1 is not enabled out of reset. --- NOTE for the last sentence: This feature requires a dedicated WDOG_B pin for it. The fact that changing the IOMUX configuration can alter the WDOG_B functionality (GPIO by default) is not ideal as it defeats the purpose of this feature. But it still takes effect when the muxed pin is configured as WDOG_B within 16 seconds. Clear PDE bit to avoid WDOG_B (aka, WDOG-1) assertion. Tested on MX6SL. May add this for other MX6x. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00220824: mx6sl_evk: mmc: only SD1 supports 8bit on evk board.Ryan QIAN2012-08-21-4/+0
| | | | | | - configure SD1 to support 8bit on evk Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217505-8 uboot: MX6Q-ARD: set the default gpmi clock to 20MHzHuang Shijie2012-08-20-3/+2
| | | | | | Set the default clock to 20MHz. The 11Mhz is too slow. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00220486 Modify ODT values for Solo AIAlejandro Sierra2012-08-20-4/+4
| | | | | | | | | | | | | | | | | | Modify ODT values for Solo AI. Some Solo boards did not passed the "mtest" from uboot using the previous configuration. Old configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) New configuration: MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00011117) MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00011117) Signed-off-by: Alejandro Sierra <b18039@freescale.com>
* ENGR00220161: imx6sl: Add MX6SL EVK SupportRobby Cai2012-08-14-0/+2074
| | | | | | | | | Add mx6sl evk board support - copied from ARM2 board support - added a new board revision - removed unused boot device detection Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00220164 pfuze:rise VDDARM_IN to 1.425V and work around pfuze1.0Robin Gong2012-08-13-0/+45
| | | | | | | | | 1.Considering pfuze tolerance and IR drop and board ripple, need rise from 1.375V to 1.425V. Only for Sabresd. 2.workaround pfuze1.0 ER1, set all buck regulator except SW1C to PWM mode. now for mx6sl_arm2 and mx6_sabresd. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00219854-1 Enable fastboot feature on mx6q-arm2 boardLiGang2012-08-09-0/+47
| | | | | | | | 1. enable fastboot feature on mx6q-arm2 board 2. enlarge fastboot buffer to 320MB 3. correct some usb descriptors Signed-off-by: LiGang <b41990@freescale.com>
* ENGR00218915-2 MX6 SabreSD:Use new 8bit bmp boot logoLiu Ying2012-08-03-5/+5
| | | | | | | | This patch changes to use new 8bit 600x400 bmp boot logo. As this boot logo has black background and white words, the user experience will be better. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218915-1 FSL common:Add new boot logoLiu Ying2012-08-03-1/+30159
| | | | | | | This patch adds new boot 8bit 600x400 bmp logo who has black background and white words. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218972 MX6 Secure Boot, Change to dynamic HAB data authenticationEric Sun2012-08-01-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original secure boot implementation make a consumption that u-boot.bin will not exceed 0x2F000. With this consumption, the hab data is hard coded in linker script file to relative address 0x2F000 without causing any problem. But when this consumption don't hold, the hard coded way will cause memory region overlap and break build. So we need to change to a dynamic way of allocating hab_data. The new implementation put hab data at the next 0x1000 alignment after u-boot data and text section, instead of hard coded to 0x2F000. Similar changes is made to uImage authentication implementation. Changes in U-Boot includes: - in u-boot.lds file, change "__hab_data" to dynamic align to 0x1000 - change authenticate_image implementation, originally the uImage parameters are hard coded, now they are retrived from the "load_addr" and the image_hdr The new secure image layout: U-Boot +-------------------+ DDR_START | | | U-Boot Image | | | +-------------------+ DDR_START + UBOOT_SIZE | PADDING | +-------------------+ align to 0x1000 | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ uImage +-------------------+ DDR_START | | | uImage | | | +-------------------+ DDR_START + UIMAGE_SIZE | PADDING | +-------------------+ align to 0x1000 | IVT | ---- Size : 0x20 +-------------------+ | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00218583-1 MX6Q/DL SabreSD:Support LVDS1 splashimageLiu Ying2012-07-31-0/+9
| | | | | | | This patch configures iomux gpr3 register to enable LVDS1 via IPU1 DI1 if user chooses to use it. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00218805 imx6: print the silicon revision correctlyJason Liu2012-07-30-11/+4
| | | | | | | | | | | | | | The silicon revision is not printed correctly, on ARM2 and sabrelite board, the log is just as the following: CPU: Freescale i.MX6 family TO0.0 at 792 MHz We need print the silicon revision correctly as: CPU: Freescale i.MX6 family TO1.2 at 792 MHz with i.mx6q TO1.2 chip Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00217401 common: fix build warningXinyu Chen2012-07-26-3/+1
| | | | | | | | | Fix the build warning in uboot build. Fix bug of incorrect dereference to periph2 clock pre divider. Fix incorrect type of maxpackage size assign, even it's not used at all in fastboot. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ENGR00218282 MX6Q: fix linker error when more configure enabled.Zhang Jiejing2012-07-25-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fix the linker error when enable more function(like CONFIG_NAND, CONFIG_SPASHSCREEN,etc) in uboot ARM2 board, and a possable linker error for other MX6 boards: /home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/ bin/arm-eabi-ld: section .bss [27831000 -> 278666e7] overlaps section .rodata [2782387c -> 278609eb] /home/lambert/share/SATA2/R13.3/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/ bin/arm-eabi-ld: section .rodata.str1.1 [278609ec -> 27867803] overlaps section .bss [27831000 -> 278666e7] One issue here is: A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. Another issue is: The secure boot feature require __hab_data section in uboot linker script, but it's have a hard coding magic number, but if we enable more code, cause .text section bigger, it will cross the line, so it report the first linker error. This commit disable SECURE_BOOT feature by default for android, and comments if user want to use this feature, it needs change the .lds by there configure. Also, enlarge the magic number that this feature needs to cover if more code is build in. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00217764 MX6 Secure Boot : Fix NAND BOOT Failure due to secure patchEric Sun2012-07-23-7/+8
| | | | | | | | | | | | | | | | | | With the secure boot patch. MX6 NAND Boot is not functional. The root cause is that, the original secure boot patch fills "0xFF' to spacing regions, due to a issue in ROM code, read pages of all "0xff" will be treated as a critical error. Thus prevent the U-Boot from booting normally. The fix adjust image copy size in IVT so that when secure boot is not enabled, no unuseful data is copied by ROM code. Also the secure boot option is default disabled. The end user won't enable it unless they know what they are doing. These prevent the ROM code from copied pages of "0xff" data, and fix the issue. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00217381-01: mx6sl add sd1 and sd2 to support SD3.0Ryan QIAN2012-07-19-2/+2
| | | | | | enable SD3.0 support on SD1 and SD2 on mx6sl arm2 cpu board. Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217114-1 MX6 U-Boot, Secure Boot, one code base for MX6Q/DL/SLEric Sun2012-07-13-171/+25
| | | | | | | | Move the secure boot related implementation code from mx6q_arm2.c to mx6/generic.c. In this way the HAB feature can be shared by all MX6 platforms Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00216852 MX6SL ARM2, UBoot : Apply V0.93 LPDDR2 ScriptEric Sun2012-07-13-17/+20
| | | | | | | | IC Validation team release new LPDDR2 script V0.93 in the following link, "http://compass.freescale.net/livelink/livelink?func=ll&objId=226733834/" Make changes to align to it Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215197 pfuze MX6SL_ARM2: enable LDO bypass on u-bootimx-android-r13.5-alphaRobin Gong2012-07-04-0/+316
| | | | | | 1.enable I2C and I2C bus recovery support on mx6sl_arm2 2.enable LDO bypass on u-boot, by configuring 'CONFIG_MX6_INTER_LDO_BYPASS' Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00215633 MX6DL LPDDR2 : enable plugin mode of system bootEric Sun2012-07-03-1/+581
| | | | | | | | | | | | | | | | | | | | | For MX6DL LPDDR2 board, in order to use both the 2 channels of the memory, the "PL301_FAST2" must be set to 0x1. However this bit is not accessible using DCD. Plugin mode must be utilized for this purpose. The patch can be verified this way: Enter U-boot console > mw.l 0x80000000 0xC0 10 > mw.l 0x10000000 0xC1 10 > md.l 0x10000000 10 > md.l 0x80000000 10 Before the patch, 0x10000000 and 0x80000000 in fact point to the same memory location. So the last 2 dump will show memory content of both 0x000000C1 After the patch, 0x80000000 ponit to channel 0, 0x10000000 point to channel 1. the last 2 dump will show memory content of 0x000000C0 and 0x000000C1 respectively Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215515 MX6: Move IPU QoS and VDOA/IPU/VPU AXI Cache config to kernelWayne Zou2012-07-02-70/+18
| | | | | | | Move IPU QoS and VDOA/IPU/VPU AXI Cache config to linux kernel in order to reduce code duplicate Signed-off-by: Wayne Zou <b36644@freescale.com>
generated by cgit v1.1 at 2024-11-25 08:24:13 +0000