| Commit message (Collapse) | Author | Age | Lines |
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CPU board (E2530) has a fan - turn it on via GPIO to keep
the SoC cool.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This was done in the 32-bit AVP loader (SPL) but is
board-specific so should be moved to the CPU portion.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
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Disable a few things which interfere with the EFI init. This allows QEMU to
to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Add support for the efi-x86 board, which supports running U-Boot as an
EFI 32-bit application.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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USB_KEYBOARD is now defined in drivers/usb/Kconfig, drop our own duplicate
definition.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Now that the musb-new driver has a Kconfig, we can move Kconfig options to
enable controllers to it, so that it's easier in e.g. menuconfig.
In addition, this allows declaring support for USB_MUSB_HOST/GADGET in
defconfigs instead of the USB_MUSB_SUNXI controller, that will get selected
automatically when needed.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Program the external regulator to switch off voltage in deep sleep.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
supports sd for usdhc2, but can do hardware rework to make usdhc2 support
emmc.
Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img
U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
- invalid sensor device
Reset cause: POR
Board: MX6UL 14x14 EVK
I2C: ready
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Refactor display code to only setup hdmi if do_enable_hdmi() is invoked.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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Add support for selecting display preset using the environment variable
"displaytype". This is a preparation for future merging of compulab
omap3_display.c display selection code with the cm-fx6 display selection code.
The "panel" environment variable is retained for backwards compatibility.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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Implement a cm-fx6 specific board_video_skip() to provide the option to not
initialize the display.
The new function does not init display if the environment variable "panel" is
not defined, or if it is set to an unsupported value.
Collateral changes:
- Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific).
- Don't use detect_hdmi(), since env controlled init makes it unnecessary.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
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U-Boot does not explicitly assign the display to an IPU interface. Instead, it
relies on the power-on default of DI0.
Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI
display no longer works in U-Boot.
Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
PMIC: PFUZE100 ID=0x10
Flash: 32 MiB
NAND: 0 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
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Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.
Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Use the same DCD settings from Congatec's U-boot tree for
the P/N 016113 card.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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Add SATA support.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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Add LVDS and HDMI support.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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Add USB support.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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cgtqmx6eval has a PFUZE100 FSL PMIC connected to I2C2.
Add support for it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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cgtqmx6eval has an eMMC connected to ESDHC3.
Add support for it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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There is no need to use multiple lines when they fit into a single line.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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Perfoming an OR operation on the error is not a good approach.
Return the error immediately for each ESDHC instance instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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Declare 'static' when possible.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
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The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should be of type 'int' instead of 'unsigned int' in order to
correctly handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Warp has a MAX77696 PMIC connected via I2C1 bus.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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This patch adds support for the "OHB System AG" baseboard
with is equipped with the TQMa6S SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
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enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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cpld reset altbank should always reset to bank4 no matter what
current bank is.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.
In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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defconfig files are added and SFP version for these platforms
is updated.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
Signed-off-by: Tom Warren <twarren@nvidia.com>
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