| Commit message (Collapse) | Author | Age | Lines |
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Move the mx6ul DDR3/LPDDR2 ARM2 boards codes from v2016.03 u-boot as
the base for OF_CONTROL enabling.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update mx6ulevk board files and build configurations to enable
OF_CONTROL and DM drivers.
1. QSPI settings and codes update for using DM QSPI driver.
For DM and non-DM driver, the AMBA address is not same.
2. Update configurations for DM i2c driver, using CONFIG_SYS_I2C for non-DM driver
3. GPIO update for adding gpio_request
4. Add FEC DM driver support for two FEC controllers.
5. Enable USB DM driver.
6. Enable 74X164 DM driver for 74LV controlling.
7. Enable PMIC DM driver for 9x9 EVK
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update mx6slevk board files and build configurations to enable
OF_CONTROL and DM drivers.
1. Update PMIC and LDO-bypass codes for DM PMIC driver.
2. Update configurations for DM i2c driver
3. GPIO update for adding gpio_request
4. Remove duplicated configurations from build config
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable FEC, USB and QSPI DM driver in build configuration and update
board file for them.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update mx6sxsabresd board files and build configurations to enable
OF_CONTROL and DM drivers.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable OF_CONTROL and DM driver on mx6qsabreauto.
1. Add the imx6qsabreauto relevant DTS file for using DTB.
2. Modify PMIC initialization codes to use DM PMIC driver.
3. Modify to use PCA953X DM driver
4. Remove NAND from default, since the default imx6q-sabreauto.dts disabled
the nand. The pins are conflicted with UART3, while UART3 is enabled.
5. For NAND build configuration, remove the USB, since the imx6q-sabreauto-gpmi-weim.dts
will have pin conflicts on steer logic.
6. GPIO requests added.
Signed-off-by: Ye Li <ye.li@nxp.com>
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1. Add build configs for i.MX6ULL 9X9 EVK. Enable DM I2C driver and
DM PMIC driver for pfuze3000. Convert power init codes to use
DM PMIC driver.
2. Add lpddr2 script IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc for
the 9x9 board.
Refer the commit 44a84b44a84cd1bdcc54d722987e5f109510891b
3. Add DTS file for 9x9 evk board.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update mx6ull evk to add features from v2016.03.
1. Add support for NAND flash.
2. Add support for QSPI DM driver.
3. Add USB DM driver support.
4. Add two FEC support by using DM FEC driver
5. Update environments for various boot devices support: SD/NAND/eMMC/QSPI
6. Add MFGtool environments.
7. Add board codes for 9x9 EVK board
For the DTS file, some changes are needed for using QSPI DM driver
1. Add spi0 alias for qspi node. Which is used for bus number 0.
2. Modify the n25q256a@0 compatible property to "spi-flash".
3. Modify spi4 (gpio_spi) node to spi5
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update mx6sll EVK board codes for features:
1. Add SD/MMC dynamical device detect.
2. Add wdog set for kernel.
3. Add mfgtool environments.
4. Modify SD/MMC environment offset.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The PHY settings for RGMII has been removed from mx6qsabreauto board codes,
due to the atheros PHY driver have updated to use same configuration for
AR8031 and AR8035, while this configuration is duplicated as we set in board codes.
But in recent codes, the PHY driver added a patch for AR8031 independent config.
So needs to add the PHY settings back to the board codes.
Signed-off-by: Ye Li <ye.li@nxp.com>
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We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fd8fbf7fa0b10199ac89cd13cae851149f51accb)
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In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
While kernel uses the clock from internal PLL by setting GPR5 bit 9.
When doing warm reset in kernel, the GPR regigster is not reset, so
the clock source still is the PLL. This causes ENET in u-boot can't work.
In this patch, we change the u-boot to use internal PLL to align with
kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 7f00c72e17e4e440df62aa4945a619fdbc9cfd8f)
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Setup MMDC in two channel fixed mode
Initialize dram banks for two channel fixed mode
DRAM bank = 0x00000000
-> start = 0x10000000
-> size = 0x20000000
DRAM bank = 0x00000001
-> start = 0x80000000
-> size = 0x20000000
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit bf1d8faf1dab7c4245ba7b79ceef6279cff45625)
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When using watchdog timeout in kernel, the reset does not output the
WDOG_B signal, so the power supply won't be reset. To solve the problem,
we enable it in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8a713e8cd1500ecc6daa02a14a63763a548095b4)
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When using watchdog timeout in kernel, the reset does not output the
WDOG_B signal, so the power supply won't be reset. To solve the problem,
we enable it in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 7b53ee014c9f02f6ead0b60d5295d07205247a7c)
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Set the ID pin pad to pull up not the pull down at default, otherwise
we can't enter the device mode, but always detect as host.
After this change we have to use portA cable to play as host,
and use portB cable for device.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit b315d6b36a913d75d25284320e69050ebdf7a7eb)
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This is a demo that CM4 will boot up by u-boot without typing any
command. It boots up at u-boot early init, try to minimize the time
from power up to the CM4 running.
Since CM4 runs on QSPI NOR XIP, we have to disable the QSPI driver in
u-boot to avoid conflict.
RDC for shared GPIO1 is added, but not enabled, because the kernel is
not ready for shared GPIO1. Users can uncomment the CONFIG_IMX_RDC to
enable it.
Some legacy codes in mx6sxsabreauto are removed. We only need this work
on mx6sxsabresd as a demo.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f66842f79d4e33ace45762466eed23a86d367642)
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Add support for various boot devices like NAND, QSPINOR, SPINOR,
eMMC, EIMNOR, SATA.
Modify board level files to support the feature and add corresponding defconfig files
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 72c35e80b86f7f75a52db45959793882bb730793)
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CONFIG_SECURE_BOOT is used for signed image building, this configuration is
not enabled at default. Comment it in mx6/mx7 common header file. Users can
uncomment it to enable.
Also add CONFIG_CSF_SIZE for defining the CSF reserved size and resize
the CONFIG_CSF_SIZE to 0x4000 to align with v2016.03.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 01cc7d9bc205251c13712418d51f3a4d7b20861b)
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Port LDO bypass support from v2015 to support the features:
1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
on the flatten device tree file.
2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
reboot whole board, so split these code to independent function so that board file
can call it freely.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5b87d04dba66fa45375d59648838ef89f559f75d)
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Align with imx_v2016.03
1. Update pmic settings to enable SD3 power and use PMIC common init codes.
2. Enable bmode.
3. Update MMC root parameters
4. Update AUXBOOT for M4
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 0816a496fbe3f7d0e4f1a9322c76908a5c557c8c)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Align with imx_v2016.03.
Add emmc support which needs board rework.
Add I2C2.
Update pmic settings.
Add bmode.
Move partial code from board_early_init_f to board_init.
Add PCI power and reset GPIO and disable PCI at default.
Update QSPI settings.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 9613a2d07760f56b3c93779b14ad32ef69856da7)
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Add elan code, to handle epdc which has i2c devices.
In imx_v2015.04, the two pathces are for elan.
b6ba68516b681a38025252bd0ef6a6ed3e8adfa0
MLK-10215 Add elan init in i.MX6SL-EVK board
0c600f6a67f00fe0c674c08c355bea3789109679
MLK-10885 imx: mx6slevk ignore elan init when no epdc on board
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit cb249aa1d57788c52145d28f2e2c68cb320d8ae3)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Align board code and header file with imx_v2016.03.
Update pmic settings for i.MX6QP.
wrap spi code together using CONFIG_MXC_SPI macro.
To i.MX6SOLO, need to define nosmp in bootargs.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit bb35d09d140efc7ff9b74bbcd77d7827c1dd503e)
Signed-off-by: Ye Li <ye.li@nxp.com>
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DDR script file:
arik_r2_sdb_ddr3_528_1.14.inc
Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1
Update:
setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10)
setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00)
setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10)
setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10)
setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10)
setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10)
setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10)
setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10)
setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
setmem /32 0x021b48c0 = 0x24914452
setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1
Test:
Passed stress memtester on one board.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)
(cherry picked from commit f521de2c5b79ab7f9b60b26cbe6a7ad50cfce9fa)
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Align ddr script with imx_v2016.03 latest ddr script.
mx6qp.cfg is 1.13 version
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 39c2989e6ba0de6b35b2d93acd9d67f889ab4b39)
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To Align with imx_v2016.03.
1. Add USDHC1 support on mother board
2. Add SPINOR flash support.
3. Add enet ref clk pinmux setting and enet settings
4. Use CONFIG_SYS_USE_EIMNOR to wrap eimnor settings.
5. update mmc board settings
6. update board_init and move nand settings to board_init, but not in
board_early_init_f
7. update pmic settings to align with datasheet.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit f05f2281548ab7b47f69b2c517eb6f85ad09a5d2)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add solo version ddr script and build target.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 54af2f744c663ac2326c1488a26fac0c4ccdad09)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Since there is already CONFIG_MX6S used for i.MX6 SOLO in u-boot codes,
we don't need to add new CONFIG_MX6SOLO. Rename the existing CONFIG_MX6SOLO
to CONFIG_MX6S.
Additional, for CONFIG_MX6S, we should select CONFIG_MX6DL. The major difference
for these two chips are core number and DDR controller. So all duallite
relevant definitions can apply to solo. User can combine the two configs
if any code only apply to solo or duallite.
Signed-off-by: Ye Li <ye.li@nxp.com>
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DDR script:
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
Patch in imx_v2015.04:
"
commit 5fb08a4dcc7b8478fc4236b90ad8dc2190cf94e7
Author: Peng Fan <Peng.Fan@freescale.com>
Date: Wed Nov 4 16:30:47 2015 +0800
"MLK-11825 imx: mx6dqp: update ddr script to 1.13"
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit d756891b9d303e456f59a18d5fa81969a7f37337)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add mx6qarm2 new board revision support using mx6q pop SoC
Enable DRAM support for imx6q PoP SoC with populated LPDDR2
MT42L128M64D2
DDR calibration script:
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69
Test result: Stress test passed.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit b0ac10892cad46c22accf89c04ea59c46bd9eb01)
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ALign with imx_v2015.04.
Also to lpddr2 support:
From commit: "620cf5f3d4cf37b065b5857a8ea91d61bf6c471d"
"
Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board,
but there is a problem in switching pre_periph_clk_sel to pll2_pfd2.
We cannot directly change the parent of pre_periph_clk_sel as this mux
is not a glitchless mux. We need to follow the correct procedure and wait
for the busy bits to clear before switching.
Change to follow the procedure:
1. Set periph_clk2 to OSC.
2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for
periph_clk , ahb_podf and axi_podf busy bits.
3. Setting the pre_periph_clk to PLL2 PFD 396M.
4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR
busy bits.
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
(cherry picked from commit febf98c68853030ce5c1f9124e77d75456e71314)
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Add the support for i.MX6DQ PoP lpddr2 ARM2 board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit e8777e91a239599ffd231ef56c60d49b68e5e3fc)
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Add plugin.S for plugin boot initialization on mx6dq/dl arm2 board.
Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature.
New build configurations are added for the plugin:
mx6dlarm2_lpddr2_plugin_defconfig
mx6dlarm2_plugin_defconfig
mx6qarm2_lpddr2_plugin_defconfig
configs/mx6qarm2_plugin_defconfig
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN"
for this feature.
Add build configurations for the plugin:
mx6ul_14x14_evk_plugin_defconfig
mx6ul_9x9_evk_plugin_defconfig
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add plugin.S for plugin boot initialization on mx6dq/dl/dqp sabresd and sabreauto
boards. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature.
Add the configurations for the plugin enabled buiding.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN"
for this feature.
Add the build configuration "mx6sxsabreauto_plugin_defconfig" to use the plugin.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN"
for this feature.
Add the build configuration "mx6sxsabresd_plugin_defconfig" to use the plugin.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN"
for this feature.
Add the build configuration "mx6slevk_plugin_defconfig" to use the plugin.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add NAND pinmux settings, clock setting and related configurations.
Default not enabled, need hardware rework.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Current i.MX6UL EVK boards enable the SPL u-boot. Change it to non-SPL
for default configurations. Add two other build configurations for SPL.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for
module fuse check. And modify board level codes for SD, FEC and EIM.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9232e9f7637afa3b71b43ab2d1361582ec5a080a)
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Add configurations and board codes for second enet.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 4dfd06dc649615f8dd3e1ac8018a0a7109fc4147)
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Add configurations and board codes for second enet.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b646262f1f201e11e08968ddf88aeb8ab41fcf21)
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Add LCD configurations and TFT43AB display settings for mx6sllevk.
Enable the CONFIG_VIDEO for this feature.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add LCD configurations and MCIMX28LCD display settings for mx6sllevk.
Enable the CONFIG_VIDEO for this feature.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Change to panel environment for display at default. Align this feature to
v2015.04 uboot.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ea93a34a3348f80462ea5b61a4ca2e9a1d267f4c)
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Support two display panels, one for LVDS, another for parallel LCD. Align
the feature to v2015.04 uboot.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit d5f7833adf6236357cf3c139e14e46d718e20524)
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Support two display panels, one for LVDS, another for parallel LCD. Align the
feature to the v2015.04 uboot.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit d7f54f22607ffcace6cda97984649a5ae4f65996)
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Dynamic setting mmcdev and mmcroot for mx7dsabresd.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 2fc0e6ccc90989375ac6355d4f33fd4ffaca9b3a)
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