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* MA-8840 picosom: change to 512M ddr ramWinter Wang2016-10-13-6/+30
| | | | | | | | | Pin GPIO5_IO01 is for detect 256M/512M version, this pin is pulled high for 512M version and low for 256M version. Just print version check message out . Signed-off-by: Winter Wang <wente.wang@nxp.com>
* MA-7633-1 [Android-SD-EMMC] enable BCB partition in androidzhang sanshan2016-04-29-1/+6
| | | | | | | | 1 Add some APIs to operate BCB/command. 2 Add action to check the command of BCB. It can cover the case that power down when do factory-reset\ota in recovery mode. Signed-off-by: zhang sanshan <b51434@freescale.com>
* MA-7717 - [pico-emmc]: support emmc pico boardfang hui2016-03-16-4/+18
| | | | | | | Change SD1 to 8-bit SD card detect is supposed to be GPIO1_19 Signed-off-by: fang hui <hui.fang@freescale.com>
* MLK-12442: imx: mx6qarm2: lpddr2 set dram 2 channel fixed modeAdrian Alonso2016-03-16-2/+11
| | | | | | | | | | | | | Setup MMDC in two channel fixed mode Initialize dram banks for two channel fixed mode DRAM bank = 0x00000000 -> start = 0x10000000 -> size = 0x20000000 DRAM bank = 0x00000001 -> start = 0x80000000 -> size = 0x20000000 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12371-2: imx: mx7dsabresd: fix POR reset failed after DDR enter retentionRobin Gong2016-03-16-0/+12
| | | | | | Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR retention mode before uboot boot, so add this in DCD and plugin code. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
* MLK-12371-1: imx: mx7d_12x12_lpddr3_arm2: fix POR reset failed after DDR ↵Robin Gong2016-03-16-2/+17
| | | | | | | | | | enter retention Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR retention mode before uboot boot, so add this in DCD and plugin code. Meanwhile correct the HW_ANADIG_SNVS_MISC_CTRL setting to avoid touching other bits. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
* MLK-12393: imx: mx6qamr2: update lpddr2 dcd programming aid settingsAdrian Alonso2016-03-16-5/+5
| | | | | | | | | | | | | | | Adjust optimal valid clock cycles for 400Mhz operation Adjust valid clock cycles before self-refresh exit tCKSRX Adjust valid clock cycles after self-refresh entry tCKSRE Set MMDC1_MPZQHWCCTRL upper 16 bits to default reset value DDR calibration script http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69 Test result: Stress test passed. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12346 imx: mx7d: switch to use DRAM_PLL, but not DRAM_ALT_CLK_ROOTPeng Fan2016-03-16-24/+79
| | | | | | | To simplify kernel clock management, we switch to use DRAM_PLL for DRAM controller and DDR PHY, but not use DRAM_ALT_CLK_ROOT. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12329-1 imx7d: Update DDR script for TO1.1Ye Li2016-03-16-24/+998
| | | | | | | | | | | | | | | | | | | | On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated. When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards), DDR data corruption occured, not able to decrease CKE delay, so we have to add extra delay on all other signals to balance it. DDR script needs to be fine-tuned according to this hardware change. For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from 533Mhz to 400Mhz. Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name Test: Overnight tests passed on all changed boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12261 MX6DQ{P}/DL:SABRESD Fix bmode eMMC failureYe Li2016-03-16-1/+1
| | | | | | | | | | The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card. Fixed the value to correct one. The issue was fixed in 2014.04 u-boot, but that patch seems missed during porting to 2015.04. Signed-off-by: Ye Li <ye.li@nxp.com>
* MA-7455 Import picosom boot codesHaoran Wang2016-03-16-0/+931
| | | | | | | | Imported the picosom boot codes and board configs from technexion. Signed-off-by: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>
* MLK-11811: imx: mx6qarm2: add new board revision supportAdrian Alonso2016-03-16-0/+294
| | | | | | | | | | | | Add mx6qarm2 new board revision support using mx6q pop SoC Enable DRAM support for imx6q PoP SoC with populated LPDDR2 MT42L128M64D2 DDR calibration script http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/e5c6184940486bcbc28978d60ad3cd996c205a08 Test result: Stress test passed. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* MLK-12034 imx: mx7dsabresd: Add RevB board supportYe.Li2016-03-16-41/+148
| | | | | | | | | | | | | Since i.MX7D SDB revB board has some HW changes, we have modify the BSP file to support new pinmux. 1. OTG2 PWR pin is changed to GPIO1_IO07. 2. A enet2_en pin is added for isolating enet2 signals with EPDC, we also add support for enet2. 3. pin6 of 74LV output is changed for CSI PWDN. Set output to high to power down it. This patch also tries to get the board id and apply changes according with it. Since current RevB board does not burn GP1 fuse for board id, we have to check the TO rev instead even it is not very exact. Will update this if any new way implemented. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-12017 imx: mx6ulevk: Update DDR script for new DDR MT41K256M16TW-107Ye.Li2016-03-16-0/+183
| | | | | | | | | | | | | | | | | | | Current Micron DDR MT41K256M16HA-125 on i.MX6UL will be EOL. Plan is i.MX6UL will use the new 20nm litho 4Gb DDR3L MT41K256M16TW-107. Update DDR script of mx6ul evk board for this new DDR, and use it as default. http://compass.freescale.net/livelink/livelink?func=ll&objId=234910940&objAction=browse&viewType=1 Test result: Stress test passed. Meanwhile add build targets below for old DDR support: mx6ul_14x14_evk_ddr_eol_android_defconfig mx6ul_14x14_evk_ddr_eol_brillo_defconfig mx6ul_14x14_evk_ddr_eol_defconfig mx6ul_14x14_evk_ddr_eol_qspi1_defconfig Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11995 ARM: imx7: add i.mx7d TO1.1 support for LPSR modeAnson Huang2016-03-16-6/+16
| | | | | | | | i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR, add support to this change for LPSR which needs to exit from DDR retension mode. Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
* MLK-11951 pfuze: Fix unsigned variable for less-than-zero comparisonYe.Li2016-03-16-1/+2
| | | | | | | | According to the Coverity result, a unsigned int variable is used fo less- than-zero comparison, the result is never true. Need to fix the variable type to signed int. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11892 imx: boards: fix variable typePeng Fan2016-03-16-7/+15
| | | | | | | ret should not use unsigned integer. Should use signed interger to compare against 0. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11825 imx: mx6dqp: update ddr script to 1.13Peng Fan2015-11-09-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI arik_r2_sdb_ddr3_528_1.13.inc is for sabresd 1.13<-1.12: Change log: 1. Remove 20c4080 1.12<-1.10 Change log: 1. NoC register DDRCONF change to 0 which is compatible for only CS0 is used on board 2. Change 2 values to compatible with our DDR aid script, these two registers doesn’t have any effect on current system tRPA = 0; //this bit only used in DDR2 mode tAOFPD/tAONPD=0x4; //These register only works when MDPDC. SLOW_PD = 1 which is 0 in script Test results: One mx6qp-sdb and one mx6qp-ard board and one mx6qp-ard board passed 60 hours memtester stress teset. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11795-02 imx: upate the pmic standby voltage for imx6qpBai Ping2015-10-30-28/+47
| | | | | | | | | | According to the latest datasheet(Rev. B, 07/2015), the VDD_SOC_IN standby voltage should be 1.05V and on i.MX6QP, we can use the PMIC 'APS' mode in standby. we add a 25mV margin to cover the IR drop and board tolerance, so the standby voltage of VDD_SOC_IN should be setting to 1.075V. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11795-01 imx: correct the vdd_arm regulator setting on imx6qpBai Ping2015-10-30-45/+101
| | | | | | | | | on i.MX6QP SDB board, the SW1A/B/C regulator is used by VDD_SOC_IN, the regulator of VDD_ARM_IN is SW2, the voltage setting for VDD_ARM_IN should be corresponding to SW2. So fix the regulator mismatch issue on i.MX6QP SDB board. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11799 imx: mx6qpsdb: update ddr script to 1.10Peng Fan2015-10-30-4/+4
| | | | | | | | | | | | | http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/963fbc75ef6d36e12819e81de23410749754e5ef http://compass.freescale.net/livelink/livelink?func=ll&objId=234709279&objAction=browse&viewType=1 Main change: (SDB board ddr density is different) 1. tRFC is different with density, tXS/tXPR refers tRFC Test Results: 2 MX6DP-SDB and 2 MX6QP-SDB boards passed overnight stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11753 imx: mx6dqp: update ddr script to v1.09Peng Fan2015-10-23-7/+17
| | | | | | | | | | | | | | | | | | | | | | ddr script update to 1.09: http://compass.freescale.net/livelink/livelink?func=ll&objId= 234694528&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.09.inc is for sabre-auto board. arik_r2_sdb_ddr3_528_1.09.inc is for sabre-sd board. Changelog: 1. Optimize DQS duty cycle setting 2. Optimize ZQ PU/PD value Test results: 2 ARD boards. 2 6QP-SDB boards. 1 6DP-SDB board. All passed overnight memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit ba8dcef9d8e10e46130559ce6defe4411bd1d1a6)
* MLK-11675 ARM: imx: change the VDD_SOC normal voltage to 0.975VBai Ping2015-10-13-0/+37
| | | | | | | | | According to the latest datasheet(Rev. C Draft 1, 10/2015) of i.MX7D, change the VDD_SOC voltage to 0.95V in run mode, and add a 25mV margin to cover the IR drop and board tolerance. So setting VDD_SOC voltage to 0.975V. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11682 imx: mx6ul: Update DDR script of 14x14 EVK board to 1.2 revYe.Li2015-10-10-21/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | IC team releases new DDR script "EVK_IMX6UL_DDR3L_400MHz_16bit_V1.2.inc", update it to DCD and plugin for i.MX6UL 14x14 EVK board. Updated items: Removed: 0x020c4084 0x021B0858 Value changed: 0x020E027C 0x020E0280 0x021B0008 0x021B000C 0x021B0010 0x021B0018 0x021B08C0 The script versions of EVK board and Validation Board from the following link: http://compass.freescale.net/livelink/livelink?func=ll&objId=234191407&obj Action=browse&viewType=1 Test Results: Two boards passed overnight memtester stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-2 imx: mx6ul: Modify the MMDC automatic Power saving timerYe.Li2015-09-30-1/+1
| | | | | | | | The PST bit can't be set too small which will cause performance drop. Refer the commit for same issue on MX6UL 9x9 EVK, now fix it for 14x14 LPDDR2 ARM2 commit e1ca547d198dde94c4d8278c99499ec2d2008880 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11662-1 imx: mx6ul: Change 14x14 LPDDR2 ARM2 memory size to 256MBYe.Li2015-09-30-1/+1
| | | | | | | The actual memory size is 256MB not 512MB, otherwise it has a wrap problem in memory and will cause memtester failed. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11622 imx6dqp-sabresd: update ddr script to v1.08Robby Cai2015-09-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable bank interleave feature to improve the performance downloaded from http://compass.freescale.net/livelink/livelink?func=ll&objId=234609508&objAction=browse&viewType=1 Before: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 15566us, 64fps, 134Mpixel/s ........ g2d blending time 20672us, 48fps, 101Mpixel/s ........ g2d blend-dim time 13616us, 73fps, 153Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 8433us, 118fps, 247Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 15366us, 65fps, 135Mpixel/s ........ 180 rotation time 15374us, 65fps, 135Mpixel/s ........ 270 rotation time 15373us, 65fps, 135Mpixel/s ........ g2d flip-h time 15373us, 65fps, 135Mpixel/s ........ g2d flip-v time 15372us, 65fps, 135Mpixel/s ........ ... After: $ /opt/fsl-samples/g2d/g2d_test Width 1920, Height 1088, Format RGBA, Bpp 32 ---------------- g2d blit performance ---------------- g2d blit time 2810us, 355fps, 743Mpixel/s ........ g2d blending time 4025us, 248fps, 518Mpixel/s ........ g2d blend-dim time 2740us, 364fps, 762Mpixel/s ........ ---------------- g2d clear performance ---------------- g2d clear time 1846us, 541fps, 1131Mpixel/s ........ ---------------- g2d rotation performance ---------------- 90 rotation time 5234us, 191fps, 399Mpixel/s ........ 180 rotation time 3176us, 314fps, 657Mpixel/s ........ 270 rotation time 5248us, 190fps, 398Mpixel/s ........ g2d flip-h time 2765us, 361fps, 755Mpixel/s ........ g2d flip-v time 3179us, 314fps, 657Mpixel/s ........ ... Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-11551 imx: mx6qpsabresd: Update DDR initialization in pluginYe.Li2015-09-16-0/+180
| | | | | | The DDR initialization in plugin needs to update conformably with DCD. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11549 imx: imx6ul: enlarge MMDC_MAPSR.PST to 16Anson Huang2015-09-15-1/+1
| | | | | | | | | MMDC auto power saving timer can NOT be too small, as enter/exit auto self-refresh mode too frequently may introduce too many latency for MMDC access, set it to 0x10, same as previous value on i.MX6. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11548 imx: imx6qp: add SabreSD board supportAnson Huang2015-09-15-0/+163
| | | | | | Add i.MX6QP SabreSD board support. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11486 imx: mx6ul 9x9 evk correct CS0_ENDPeng Fan2015-09-04-2/+2
| | | | | | | The lpddr2 memsize of mx6ul_9x9_evk is 256MB, not 512M, so the CS0_END should be 0x47, but not 0x4F. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11490 ARM: imx: imx6ul: disable pfuze3000 low power modeAnson Huang2015-09-02-0/+5
| | | | | | | Disable PFuze3000 low power mode during standby mode, otherwise, if the power consumption exceed the threshold, PFuze will reboot. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11427 imx: mx7d: Update DDR script for mx7d sabresd boardYe.Li2015-09-01-23/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated items: memory set 0x307a0000 32 0x03040001 --> memory set 0x307a0000 32 0x01040001 This is just enable when LPDDR4 is enabled . memory set 0x307a0064 32 0x0040005e --> memory set 0x307a0064 32 0x00400046 T_RFC_MIN this should be: RU(260ns*528Mhz)/2=69 (0x45) memory set 0x307a00d0 32 0x00020001 --> memory set 0x307a00d0 32 0x00020083 PRE_CKE_X1024 be (500us*528Mhz/2)/1024 = 129, or 0x81 memory set 0x307a00d4 32 0x00010000 --> memory set 0x307a00d4 32 0x00690000 DRAM_RSTN_X1024 (200us*528Mhz)/1024=104, or 0x68 memory set 0x307a00e4 32 0x00090004 --> memory set 0x307a00e4 32 0x00100004 DEV_ZQINIT_X32 . Should be 16 clocks memory set 0x307a0100 32 0x0908120a --> memory set 0x307a0100 32 0x09081109 T_FAW=(40ns*528Mhz)/2)=11 memory set 0x307a0104 32 0x0002020e --> memory set 0x307a0104 32 0x0007020d tXPDLL=24ns*528Mhz=13clocks File: MX7D_EVK_DDR3_1GB_32bit.ds Test result: 3 boards pass 2 days stress test. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11461 imx: imx6ul: enable LDO bypass for 9x9 EVK boardAnson Huang2015-09-01-11/+50
| | | | | | | i.MX6UL-9x9-EVK board has PFUZE3000, so enable LDO bypass support for this board. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11388 imx: mx7d: add support for mx7d 19x19 lpddr2 arm2 boardYe.Li2015-08-20-1/+274
| | | | | | | | | | This mx7d 19x19 lpddr2 arm2 board is based on 19x19 lpddr3 arm2 board with DDR changed to 512M LPDDR2. We added DDR script for LPDDR2 and a new u-boot build target: mx7d_19x19_lpddr2_arm2_config LPDDR2 script source: lpddr2_0_1.ds Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11364 imx: mx6ul : Add support for i.MX6UL 9x9 EVK boardYe.Li2015-08-17-3/+287
| | | | | | | | | | | | | | The i.mx6ul 9x9 EVK shares the same base board with 6ul 14x14 EVK with two main changes on CPU board: 1. Change to use pfuze 3000. 2. Use 256MB LPDDR2 memory. This patch uses a macro CONFIG_6UL_9X9_LPDDR2 to distinguish the changes above, basing on 14x14 EVK board level codes. The new build target for the 9x9 EVK: mx6ul_9x9_evk_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11320 ARM: imx7d: disable wdog powerdown timer for LPSRAnson Huang2015-08-05-0/+5
| | | | | | | | In LPSR mode, wdog will be reset when resume, need to disable wdog powerdown timer to avoid system reset after timeout setting of 16 seconds. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11281-1 ARM: imx7d: add lpsr resume support for imx7dAnson Huang2015-08-05-0/+343
| | | | | | | | | | | | For imx7d 12x12-lpddr3-arm2 board, when system enters LPSR mode and waked up, ARM core will be reset and uboot needs to be executed first, the LPSR register contains a resume entery, if this entry is non-zero, then it means it is a resume from LPSR mode, uboot plug in code needs to make DRAM exit from retention mode then jump to the entry directly, otherwise, it is a cold boot, normal boot process will be performed. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11263-2 video: epdc: move setup_waveform_file to board commonPeng Fan2015-08-03-144/+36
| | | | | | | | | | | Since setup_waveform_file in different boards code have same implementation, move setup_waveform_file to board common code. Also rename it to board_setup_waveform_file This patch also fix a bug when using flush_cache. We should pass 'waveform_buf' to flush_cache, but not a string named 'addr'. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11263-1 video: epdc: support display logo on E-Ink screenPeng Fan2015-08-03-0/+184
| | | | | | | | | | | | | | | | | | | Support draw image on E-ink screen. 1. The image format should be PGM-P5 raw data format. 2. The image should be named epdc_logo.pgm. 3. If no epdc_logo.pgm found in the first partition(FAT), will choose to draw black border on the screen. 4. Default configuration is to draw image at pos (0,0). If 'splashpos' env is set, will choose the pos from 'splashpos'. 5. The image size should not be bigger than screen total pixel size. 6. Implement board_setup_logo_file in board/freescale/common/epdc_setup.c 7. Introudce function prototype for board_setup_logo_file. Note: i.MX7D EPDC supports advanced mode and standard mode. Since current PXP in uboot for i.MX7D not ready, only support standard mode now. advanced and standard mode needs waveform firmware's support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11299 ARM: imx7d: initialize PMIC standby mode and voltageAnson Huang2015-08-03-0/+67
| | | | | | | Datasheet Rev-B defines standby voltage as 1V for i.MX7D, we add 25mV for board level IR drop. Signed-off-by: Anson Huang <b20788@freescale.com>
* MLK-11304 MX6 SabreSD: Disable HDMI detectPeng Fan2015-07-31-1/+1
| | | | | | | | | | | | | | | As the HDMI splash screen feature is not well supported, we should not set it to be the default display. In case, users leave the 'panel' uboot environment variable empty and connect the board with a HDMI monitor, the HDMI detect funtion will work and enable the HDMI splash screen. So, this patch disables HDMI detect function so that users may only explicitly set the 'panel' variable to be 'HDMI' to use HDMI splash screen. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11275 imx: mx6ul: Fix otg1 id pin pad setting on 6ul DDR3 ARM2Ye.Li2015-07-22-1/+1
| | | | | | | | | This pin is missed to change in patch: "MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull up" Should set it to pull down at default. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11270 ARM: imx: correct the pmic standby voltage of sw1ab on i.mx6ulBai Ping2015-07-22-2/+2
| | | | | | | The SW1AB on PMIC is used for ARM_SOC_IN supply, set the standby voltage to 0.975V to save power when system is in DSM mode. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11238 imx: mx7d fix usdhc pad settingsPeng Fan2015-07-13-35/+24
| | | | | | | | | | | | | | | | | | | To CD/VSELECT/RST, should use same pad settings with USDHC_PAD_CTRL, because default NO_PAD_CTRL's settings is 100K Pull-Down. But, we need pull-up for CD/VSELECT/RST. Also some board provides external pull-down/up, we'd better use internal pull-up for these pad settings. To mx7d_12x12_lpddr3_arm2: If no card plugged in, "mmc dev 1" will show "Card did not respond to voltage select". After apply this patch, it will show "MMC: no card present". To mx7dsabresd: Alougth without this patch, if no card plugged in sd1, still correct msg "MMC: no card present", anyway we'd better use pull-up. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11228-1 android: Integrate community fastboot with FSL i.MX fastbootYe.Li2015-07-13-164/+80
| | | | | | | | | | | | | | | | | | | | | 1. Replace the UDC driver with community's USB gadget d_dnl driver. 2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and EFI partitions are not support by i.MX. 3. Add FDT support to community's android image. 4. Change the booti command to boota, due to the booti has been used for ARM64 image boot. 5. Modify boota implementation to load ramdisk and fdt to their loading addresses specified in boot.img header, while bootm won't do it for android image. 6. Modify the android image HAB implementation. Authenticate the boot.img on the "load_addr" for both SD and NAND. 7. Enable new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot with relevant header file "fsl_fastboot.h". While disabling the configuration, the community fastboot is used. 8. Use community's way to combine cmdline in boot.img and u-boot environment, not overwrite the cmdline in boot.img Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11237 imx: mx6qpsabreauto update ddr script to 1.07Peng Fan2015-07-13-2/+8
| | | | | | | | | | | | | | | Update ddr script to version 1.07: 1. Change MDCCR from default value to 0x24912492, it will improve DDR duty cycle 2. The MMDC reorder bypass option, which has better DRAM performance URL: http://compass.freescale.net/livelink/livelink?func=ll&objId=234335046&objAction=browse&viewType=1 Test Results: 3 boards passed 48 hours memtester stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull upYe.Li2015-07-09-14/+54
| | | | | | | | | | Set the ID pin pad to pull up not the pull down at default, otherwise we can't enter the device mode, but always detect as host. After this change we have to use portA cable to play as host, and use portB cable for device. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11227 imx: mx6ul_14x14_lpddr2_arm2 add weimnor defconfigPeng Fan2015-07-09-0/+6
| | | | | | | | | | | | | 1. Add weimnor boot defconfig 2. move CONFIG_FSL_USDHC and CONFIG_VIDEO to board header 3. Add CONFIG_SYS_FLASH_PROTECTION for mx6ul 14x14 lpddr2 arm2 4. correct CONFIG_SYS_FLASH_SECT_SIZE and CONFIG_SYS_MAX_FLASH_SECT 5. Add comments for setup_eimnor, since ENET2_RXER pin conflicts with ENET2. Also eimnor support will disable SD1/SD2, need ENET to boot kernel and nfs using enet. So setup_eimnor should be invoked after setup_fec Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11217 imx: mx6ul: Modify QSPI PAD DSE to 120ohmYe.Li2015-07-03-3/+3
| | | | | | | | The current pad DSE for QSPI is 60ohm. Per hardware team measurement, this setting cause too strong drive to clock and data signals. Need to change the DSE to 120ohm for better signal quality. Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-11-22 11:42:50 +0000