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* mpc85xx: Adding more registers and optionsYork Sun2011-01-19-4/+4
| | | | | | | | | | | | | This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.hKumar Gala2011-01-19-92/+3
| | | | | | | | | | | Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr codeKumar Gala2011-01-14-16/+2
| | | | | | | | Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Convert SBC8641 to use common SRIO init codeKumar Gala2011-01-14-1/+0
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* powerpc/86xx: Convert MPC8641HPCN to use common SRIO init codeKumar Gala2011-01-14-4/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Convert MPC8569MDS to use common SRIO init codeKumar Gala2011-01-14-2/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Convert MPC8568MDS to use common SRIO init codeKumar Gala2011-01-14-2/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Convert MPC8548CDS to use common SRIO init codeKumar Gala2011-01-14-9/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-14-44/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-116/+2
| | | | | | | Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-45/+13
| | | | | | | | | Remove duplicated code in SBC8548 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-65/+2
| | | | | | | | | Remove duplicated code in SBC8641 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Paul Gortmaker <paul.gortmaker@windriver.com>
* powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-64/+16
| | | | | | | | Remove duplicated code in MPC8610HPCD board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-62/+2
| | | | | | | | Remove duplicated code in P1_P2_RDB boards and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-41/+2
| | | | | | | | Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-39/+14
| | | | | | | | Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-37/+13
| | | | | | | | Remove duplicated code in TQM 85xx boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: wd@denx.de
* powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-137/+13
| | | | | | | | Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Peter Tyser <ptyser@xes-inc.com>
* powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-41/+12
| | | | | | | | Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-53/+2
| | | | | | | | Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-102/+14
| | | | | | | Remove duplicated code in MPC8536DS board and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-83/+26
| | | | | | | | | | | | Remove duplicated code in MPC8544DS board and utilize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-111/+2
| | | | | | | | | Remove duplicated code in P2020DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-89/+10
| | | | | | | | | Remove duplicated code in MPC8572DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-pci: Add generic code to setup PCIe controllersKumar Gala2011-01-14-65/+2
| | | | | | | | | | | | | | | | | | Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx DDR: align informational printsBecky Bruce2011-01-14-16/+18
| | | | | | | | | | | | | | | | | | | | Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: rename sdram_init() lbc_sdram_init()Becky Bruce2011-01-14-16/+7
| | | | | | | | sdram_init() is used to initialize sdram on the lbc. Rename it accordingly. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx boards: initdram() cleanup/bugfixBecky Bruce2011-01-14-820/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* tqm85xx: create fixed_sdram() to do sdram setupBecky Bruce2011-01-14-14/+23
| | | | | | | | | | | Also, change this code to use phys_size_t instead of long int. Using common naming for this function will enable us to use the common initdram() for 85xx going forward. Other than the type change, this is just a code rearrange. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Cleanup SGMII detection and reportingKumar Gala2011-01-14-58/+40
| | | | | | | | Use new is_serdes_configured to determine if TSECs are in SGMII mode and report that on the various boards that use or can be configured in SGMII mode in board_eth_init() instead of in the PCI init code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configuredKumar Gala2011-01-14-41/+39
| | | | | | | Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for booting from NAND on MPC8572DSKumar Gala2011-01-14-2/+20
| | | | | | | | Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting from NAND. Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* socrates: rename sdram_setup fixed_sdram()Becky Bruce2011-01-14-2/+2
| | | | | | | | | This will help us go to a fixed initdram() for all 85xx boards going forward. sdram_setup() had an argument that it didn't need, since the value was #defined. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Remove support for PM854/PM856 boardsKumar Gala2011-01-14-1353/+0
| | | | | | | | The PM854/PM856 boards are no longer maintained and thus we are removing support for them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/85xx: Removed support for MPC8540EVAL boardKumar Gala2011-01-14-1383/+0
| | | | | | | The MPC8540EVAL board is no longer maintained and thus we are removing support for it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Removed support for ATUM8548 boardKumar Gala2011-01-14-588/+0
| | | | | | | The ATUM8548 board is no longer maintained and thus we are removing support for it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2011-01-12-0/+220
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| * sh: Add support T-SH7706LSR boardNobuhiro Iwamatsu2011-01-06-1/+1
| | | | | | | | | | | | | | | | | | | | This patch supports T-SH7706LSR board. This is constitution almost same as shmin (T-SH7706LAN). Therefore, most functions work by a change of the setting of config. http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706LSR.htm Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Fix build of shmin boardNobuhiro Iwamatsu2011-01-11-1/+1
| | | | | | | | | | | | Change lib$(BOARD).a to lib$(BOARD).o Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: Add support shmin boardNobuhiro Iwamatsu2011-01-11-0/+220
| | | | | | | | | | | | | | | | | | | | | | This adds support for the SHMIN SH7706 board(T-SH7706LAN). The CPU of this board is SH7706. There are SDRAM of 32M byte, Flash memory of 512K byte, Serial, 10Base Ether and MMC. http://web.kyoto-inet.or.jp/people/takagaki/T-SH7706/T-SH7706.htm Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | xilinx-ppc4xx-generic: Fix Makefile to work with MAKEALLRicardo Ribalda Delgado2011-01-11-18/+7
| | | | | | | | | | | | | | | | | | config.mk only mkdirs $(obj), but we have objects shared with other boards located on other dirs. This patch mkdirs the needed dirs for the xlnx-generic boards. Signed-off-by: Stefan Roese <sr@denx.de>
* | PPC4xx: Reduce NAND TLB window size on CanyonlandsFelix Radensky2011-01-10-1/+1
|/ | | | | | | 16MiB NAND TLB window is way too big. Reduce it to 1KiB. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* miiphy: convert to linux/mii.hMike Frysinger2011-01-09-71/+71
| | | | | | | | The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* tqm5200.c: fix warning: 'edid_buf' defined but not usedWolfgang Denk2011-01-09-1/+2
| | | | | | | | Commit 98e6956 "mpc52xx: add support for tqm52xx based board charon" caused build warnings on some systems. Fix these. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
* Merge branch 'next' of ../nextWolfgang Denk2010-12-22-1573/+1160
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| * 74xx_7xx/mpc86xx/ppmc7xx: Fix do_reset() declarationPeter Tyser2010-12-17-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following commit: commit 882b7d726febe65579d6502c271412ecb05821d7 Author: Mike Frysinger <vapier@gentoo.org> Date: Wed Oct 20 03:41:17 2010 -0400 do_reset: unify duplicate prototypes missed the 74xx_7xx and mpc86xx arches and the ppmc7xx board do_reset() functions which resulted in build errors such as: cpu.c:128: error: conflicting types for 'do_reset' include/command.h:102: error: previous declaration of 'do_reset' was here Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * xilinx-ppc4xx-generic: Use common u-boot.ldsRicardo Ribalda Delgado2010-12-17-548/+6
| | | | | | | | | | | | | | Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Update lwmon5 board supportStefan Roese2010-12-17-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the following changes for the lwmon5 board support: - Enable cache in SDRAM - Use common EHCI driver instead of the PPC4xx specific OHCI driver This can be done since only high-speed devices are connected. - Remove cached TLB entry again after ECC setup - Use correct define for cache enabling (CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE) - Enable FIT image support Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: t3corp: Add support for the Xilinx DS617 flash chipStefan Roese2010-12-17-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | The t3corp board has an Xilinx DS617 flash chip connected to the onboard FPGA. This patch adds support for these chips. Board specific flash accessor functions are needed, since the chips can only be read correctly in 16bit mode. Additionally the FPGA chip-selects are configured for device-paced transfers (ready is enabled). Signed-off-by: Stefan Roese <sr@denx.de>
| * Armada100: Add Board Support for Marvell Aspenite-DBPrafulla Wadaskar2010-12-16-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aspenite is a Development Board for ASPEN/ARMADA168(88AP168) with * Processor upto 1.2GHz * Parallel 1Gb x8 DDR2-1066 MHz * 16 Mb x16 NOR, 4Gb x8 SLC NAND, footprint for SPI NOR * Footprints for eMMC/eSD NAND & MMC x8 card * 4-in-1 card reader (xD, MMC/SD/MS Pro), CF True IDE socket * SEAF memory board, subset of PISMO2 With Peripherals: * 4.3” WVGA 24-bit LCD * Audio codecs (AC97 & I2S), TSI * VGA camera * Video in via 3 RCA jacks, and HDMI type C out * Marvell 88W8688 802.11bg/BT module * GPS RF IC * Dual analog mics & speakers, headset jack, LED, ambient light sensor * USB2.0 HS host (A), OTG (micro AB) * FE PHY, PCIE Mini Card slot * GPIO, GPIO expander with DIP switches for easier selection UART serial over USB, CIR This patch adds basic board support with DRAM and UART functionality The patch is tested for boot from DRAM using XDB Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
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