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* board: powerpc: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-5734/+525
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de>
* board: arm: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-4091/+289
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@ti.com>
* blackfin: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-725/+43
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Sonic Zhang <sonic.zhang@analog.com>
* m68k: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-483/+23
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Jason Jin <Jason.jin@freescale.com>
* x86: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-20/+1
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org>
* nios2: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-69/+7
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Thomas Chou <thomas@wytron.com.tw>
* nds32: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-60/+3
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Macpaul Lin <macpaul@gmail.com>
* mips: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-139/+18
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* microblaze: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-21/+1
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com>
* openrisc: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-20/+1
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* avr32: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-140/+7
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
* sh: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-427/+40
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* sparc: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-108/+5
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Hellstrom <daniel@gaisler.com>
* drivers: move some drivers to drivers/MakefileMasahiro Yamada2013-10-31-3/+2
| | | | | | | | This commit moves some drivers subdirectory entry from the toplevel Makefile to drivers/Makefile using Kbuild descending feature. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* board: ti: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-346/+22
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
* sandbox: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-20/+1
| | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* mpc85xx: introduce the kmp204x reference design supportValentin Longchamp2013-10-24-0/+687
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix ddr.c] Acked-by: York Sun <yorksun@freescale.com>
* fsl/mpc85xx: define common serdes_clock_to_string functionValentin Longchamp2013-10-24-74/+0
| | | | | | | | | | | | This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix t1040qds.c] Acked-by: York Sun <yorksun@freescale.com>
* KM: add CONFIG_KM_COMMON_ETH_INIT for km common eth initValentin Longchamp2013-10-24-0/+2
| | | | | | | | | | | | This must be defined by a board support file that want to use the keymile common.c board_eth_init function that requires ethernet_present to be defined. Currently all the km architectures use it but the kmp204x architecture later supported in this series does use another board_eth_init function and thus does not define it. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* KM: define CONFIG_SYS_I2C_INIT_BOARD only for concerned boardValentin Longchamp2013-10-24-25/+0
| | | | | | | | | | | | | This must be defined for all the keymile boards that use the common i2c_abort function that is used to "reset" the I2C bus. These are currently km82xx and km_arm boards. The km83xx boards use other functions and thus do not need this. This patch removes the CONFIG_SYS_I2C_INIT_BOARD from keymile-common.h and defines it for km_arm.h and km82xx.h. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/c29xpcie: add DDR ECC on off config settingPo Liu2013-10-24-0/+8
| | | | | | | | | | c29xpcie REV_A board DDR ECC chip has bad impedance in hardware, force that kind of board to be DDR ECC off when booting. Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on in uboot enviroment. Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* usb: rename board_usb_init_type to usb_init_typeTroy Kisky2013-10-22-1/+1
| | | | | | | | | commit bba679144d25b91bcd7befff5a96728a30875f54 "usb: rename board_usb_init_type to usb_init_type" missed xhci-omap.c So, fix that patch here, and fix a checkpatch warning. WARNING: Avoid unnecessary line continuations Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-10-21-111/+199
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| * usb: ehci-hcd: add enum usb_init_type parameter to ehci_hcd_init.Troy Kisky2013-10-20-7/+14
| | | | | | | | | | | | | | This paramter will later be used to initialize OTG ports in host or device mode. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * usb: add enum usb_init_type parameter to usb_lowlevel_initTroy Kisky2013-10-20-1/+1
| | | | | | | | | | | | This parameter will later be used to verify OTG ports. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * usb: rename board_usb_init_type to usb_init_typeTroy Kisky2013-10-20-17/+17
| | | | | | | | | | | | | | | | | | | | This will be used by usb_lowlevel_init so it will no longer be used by only board specific functions. Move definition of enum usb_init_type higher in file so that it will be available for usb_low_level_init. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * ARM: omap5-evm: Move MAC creation to misc_initDan Murphy2013-10-20-19/+20
| | | | | | | | | | | | | | | | | | Move the MAC creation from the USB init to an function that is called on every boot. This will then populate the usbethaddr mac that kernel driver can pick up from the device tree blob. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * usb: dra7xx: Add support for dra7xx xhci USB hostDan Murphy2013-10-20-6/+1
| | | | | | | | | | | | | | | | | | | | | | Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * usb: omap5: Update the board_usb_init apiDan Murphy2013-10-20-1/+1
| | | | | | | | | | | | | | | | | | | | Recent patches declares board_usb_init function prototype for a new usb architecture. Turning on the OMAP_XHCI defines cause a redefinition compiler failure. So update the board_usb_init to the latest prototype. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * samsung:common:thor: Define common Samsung code to handle THOR usb ↵Lukasz Majewski2013-10-20-0/+22
| | | | | | | | | | | | | | | | | | | | | | descriptor setup Special, common to Samsung, function for altering usb descriptor's idVendor and idProduct has been added. For compatibility reasons (Win vs Linux) the THOR idProduct must be different than the one for DFU/UMS. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * usb:g_dnl: Add name parameter to g_dnl_bind_fixup functionLukasz Majewski2013-10-20-1/+1
| | | | | | | | | | | | | | | | | | New parameter, namely *name has been added to g_dnl_bind_fixup(). It is necessary (for compatibility reasons) to assign new USB idProduct and idVendor for different usb functions. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * usb: new board-specific USB init interfaceMateusz Zalega2013-10-20-35/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit unifies board-specific USB initialization implementations under one symbol (usb_board_init), declaration of which is available in usb.h. New API allows selective initialization of USB controllers whenever needed. Signed-off-by: Mateusz Zalega <m.zalega@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * nitrogen6x: add otg usb host/device mode supportTroy Kisky2013-10-20-0/+26
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * mx6: iomux: add GPR1 defines for use with nitrogen6xTroy Kisky2013-10-20-0/+7
| | | | | | | | | | | | Select GPIO1 as the USB OTG ID pin for Nitrogen6x Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * OMAP5-uevm: USB: Add xHCI host contoller supportDan Murphy2013-10-20-23/+51
| | | | | | | | | | | | | | Add the call back into the board file for to enable the SMPS10 VBUS regulator. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * exynos: dts: Add USB VBUS GPIOs to the device treeJulius Werner2013-10-20-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new samsung,vbus-gpio parameter to the device tree, in preparation of replacing the currently hardcoded VBUS GPIO mechanism in exynos5-dt.c with a device tree controlled solution, just as it already exists in the Linux kernel. Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * exynos: usb: Switch USB VBUS GPIOs to be device tree configuredJulius Werner2013-10-20-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Exynos boards, such as the SMDK5250, control USB port power through a GPIO pin. For now this had been hardcoded in the exynos5-dt board file, but not all boards use the same pin, requiring local changes to support different boards. This patch moves the GPIO initialization into the USB host controller drivers which they belong to, and uses the samsung,vbus-gpio parameter in the device tree to configure it. Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLDPrabhakar Kushwaha2013-10-16-4/+4
| | | | | | | | | | | | | | | | NAND,CPLD AMASK register is programmed for 64K size. so Update TLB & LAW size accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-paShengzhou Liu2013-10-16-6/+170
| | | | | | | | | | | | | | | | | | | | | | | | - Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization. For more details, see board/freescale/p1010rdb/README. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix conflicts in boards.cfg] Acked-by: York Sun <yorksun@freescale.com>
* | board/p1010rdb: add pin mux and sdhc support in any bootShengzhou Liu2013-10-16-20/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pins multiplexing, SDHC shares signals with IFC, with this patch: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROMShengzhou Liu2013-10-16-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS. This patch doesn't impact on previous existing boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | powerpc/p1010rdb: remove unused cpld_showShengzhou Liu2013-10-16-35/+0
| | | | | | | | | | | | Function cpld_show() was for debug and not called, so clean it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha2013-10-16-1/+843
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
* | powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-16-177/+177
| | | | | | | | | | | | | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | powerpc/B4860: enable PBL tool for B4860Shaohui Xie2013-10-16-0/+34
| | | | | | | | | | | | | | | | Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* | powerpc/t4240: updated rcw_cfg to align with default hardware configurationShaohui Xie2013-10-16-4/+4
| | | | | | | | | | | | | | | | | | Default configuration has been changed, the most important one is DDR ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to change from 24x to 12x to keep the DDR frequency. There are also some other optimise to align with default configuration. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* | powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand bootYing Zhang2013-10-16-79/+27
| | | | | | | | | | | | Enable TPL for p1_p2_rdb_pc nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPLYing Zhang2013-10-16-0/+9
| | | | | | | | | | | | Enable p1_p2_rdb_pc to start from eSPI with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPLYing Zhang2013-10-16-12/+110
| | | | | | | | | | | | Enable p1_p2_rdb_pc to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII modeZhao Qiang2013-10-16-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix PHY addresses for QSGMII Riser Card working in SGMII mode on board P3041/P5020/P4080/P5040/B4860. QSGMII Riser Card can work in SGMII mode, but having the different PHY addresses. So the following steps should be done: 1. Confirm whether QSGMII Riser Card is used. 2. If yes, set the proper PHY address. Generally, the function is_qsgmii_riser_card() is for step 1, and set_sgmii_phy() for step 2. However, there are still some special situations, take P5040 and B4860 as examples, the PHY addresses need to be changed when serdes protocol is changed, so it is necessary to confirm the protocol before setting PHY addresses. Signed-off-by: Zhao Qiang <B45475@freescale.com>
generated by cgit v1.1 at 2024-11-17 16:04:41 +0000