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* Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-12-10-0/+54
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| * sandbox: spi: Add new SPI flash driverMike Frysinger2013-12-09-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a SPI flash driver which simulates SPI flash clients. Currently supports the bare min that U-Boot requires: you can probe, read, erase, and write. Should be easy to extend to make it behave more exactly like a real SPI flash, but this is good enough to merge now. sjg@chromium.org added a README and tidied up code a little. Added a required map_sysmem() for sandbox. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-12-10-17/+41
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| * | driver:i2c:s3c24x0: adapt driver to new i2cPiotr Wilczek2013-12-05-17/+41
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Heiko Schocher <hs@denx.de> CC: Inderpal Singh <inderpal.singh@linaro.org> CC: David Müller <d.mueller@elsoft.ch> CC: Chander Kashyap <k.chander@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
* | powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROMPo Liu2013-12-04-0/+13
|/ | | | | | | | | | Currently, there is only one EEPROM on c29xpcie board which is AT24C1024. We program the SPD data at beginning of the AT24C1024.But the AT24C1024 has a 16-bit sub-address mode. This patch is tomake it work when getting SPD in a 16-bit sub-address EEPROM. Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-12-02-0/+12
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| * malta: enable PIIX4 SERIRQPaul Burton2013-11-26-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Whilst U-boot does not require this itself, Linux currently relies upon it having been muxed and enabled by the bootloader. Thus in order to preserve compatibility with current kernels before a fix is merged in Linux we will enable the SERIRQ interrupt and mux it to its pin. Without doing this current kernels will never receive serial port interrupts and the end result is typically that userland appears to hang. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-12-02-162/+1543
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| * t2080qds/ramboot: enable PBL tool for t2080qdsShengzhou Liu2013-11-25-0/+49
| | | | | | | | | | | | | | | | Add the default RCW(SerDes 0x66_0x16) and PBI configure file for T2080QDS board, so we can use PBL tool to generate the ramboot image to support boot from NAND/SPI/SD. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * powerpc/t2080qds: add support for t2080qds boardShengzhou Liu2013-11-25-0/+1322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The T2080QDS is a high-performance computing evaluation, development and test platform supporting the T2080 QorIQ Power Architecture processor. T2080QDS feature overview Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz Memory: - Single memory controller capable of supporting DDR3 and DDR3-LV devices - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - Four 10Gbps XFI on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) PCIE: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) SATA: - Two SATA 2.0 ports on-board SRIO: - Two Serial RapidIO 2.0 ports up to 5 GHz eSDHC: - Supports SD/SDHC/SDXC/eMMC Card I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: removed Makefile blank line at EOF, fix conflicts with moving DDR driver] Acked-by: York Sun <yorksun@freescale.com>
| * Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-3/+3
| | | | | | | | | | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
| * Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-24/+34
| | | | | | | | | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
| * Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-146/+146
| | | | | | | | | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-11-25-15/+4
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| * | am335x: fix GPMC config for NAND and NOR SPL bootpekon gupta2013-11-21-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | sama5d3xek: support larger than 4G nand flashWu, Josh2013-11-21-2/+3
| | | | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com>
* | | board: tqm5200: delete its own object make ruleMasahiro Yamada2013-11-25-3/+0
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | board: h2200: Delete an unnecessary make ruleMasahiro Yamada2013-11-25-3/+0
| |/ |/| | | | | | | | | | | We have a generic rule to generate .o file from *.S in $(TOPDIR)/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: rename all libraries to built-in.oMasahiro Yamada2013-11-17-68/+68
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: make directories by Makefile.buildMasahiro Yamada2013-11-17-239/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: specifiy an explicite object name rather than $(BOARD).oMasahiro Yamada2013-11-17-3/+3
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | board: Do not add -DCONFIG_SYS_TEXT_BASE in board config.mkMasahiro Yamada2013-11-17-55/+5
| | | | | | | | | | | | | | Board config.mk do not need to add -DCONFIG_SYS_TEXT_BASE to CPPFLAGS because the top level config.mk does instead. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | nios2: remove unnecessary header include pathMasahiro Yamada2013-11-15-6/+0
| | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Thomas Chou <thomas@wytron.com.tw>
* | board: cogent: include header files in a more natural wayMasahiro Yamada2013-11-15-21/+9
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-11-14-2/+912
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| * | powerpc/t104xrdb: Add T1042RDB_PI board supportPriyanka Jain2013-11-13-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Two on-board RGMII 10/100/1G ethernet ports. - SERDES Connections, 8 lanes supporting: — PCI — SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Video - DIU supports video at up to 1280x1024x32bpp - HDMI connector - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| * | powerpc/t104xrdb: Add T1040RDB board supportPriyanka Jain2013-11-13-0/+650
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040RDB is Freescale Reference Design Board supporting the T1040 QorIQ Power Architecture™ processor. T1040RDB board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefile] Acked-by: York Sun <yorksun@freescale.com>
| * | powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pbShengzhou Liu2013-11-13-2/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove duplicate doc/README.p1010rdb - Rename README to README.P1010RDB-PA - Add new README.P1010RDB-PB P1010RDB-PB is a variation of previous P1010RDB-PA board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * | powerpc/t1040: enable PBL tool for T1040Prabhakar Kushwaha2013-11-13-0/+34
| |/ | | | | | | | | | | | | | | Use a default RCW of protocol 0x66. A PBI configure file which uses CPC as 256KB SRAM. It can be used by PBL tool on T1040 to build a pbl boot image. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | i2c, omap24xx: convert driver to new mutlibus/mutliadapter frameworkHeiko Schocher2013-11-13-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Tom Rini <trini@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Thomas Weber <weber@corscience.de> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Luca Ceresoli <luca.ceresoli@comelit.it> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Nishanth Menon <nm@ti.com> Cc: Pali Rohár <pali.rohar@gmail.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Michael Jones <michael.jones@matrix-vision.de> Cc: Raphael Assenat <raph@8d.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Stefano Babic <sbabic@denx.de>
* | i2c: sh_i2c: Update to new CONFIG_SYS_I2C frameworkNobuhiro Iwamatsu2013-11-13-3/+1
|/ | | | | | | | This updates to new I2C framwwork on sh_i2c. And this also updates boards(kzm9g and ecovec) that using sh_i2c. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* cm_t35: use scf0403 driverNikita Kiryanov2013-11-12-2/+56
| | | | | | | | Use scf0403 driver to add scf0403x LCD support for cm-t35 and cm-t3730 boards. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* MPC824x: remove obsolete "PN62" boardWolfgang Denk2013-11-11-689/+0
| | | | | | | | | | | The MPC824x processors have long reached EOL, and the PN62 board has not seen any board-specific updates for more than a decade. It is now causing build issues. Instead of wasting time on things nobody is interested in any more, we rather drop this board. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@grandegger.com> cc: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-11-11-117/+566
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| * malta: add script & instructions to flash U-bootPaul Burton2013-11-09-0/+40
| | | | | | | | | | | | | | | | | | | | This patch adds a script which may be used with MIPS Navigator Console and a MIPS Nagivator Probe in order to flash U-boot to a MIPS Malta development board. Please see the newly added doc/README.malta for usage instructions. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: setup PIIX4 interrupt routePaul Burton2013-11-09-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: enable RTC supportPaul Burton2013-11-09-0/+8
| | | | | | | | | | | | | | | | | | This is actually required in order for a Linux kernel to boot successfully on a physical Malta board. Without enabling the RTC, a Malta Linux kernel will get stuck in its estimate_frequencies function on boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: disable L2 cachesPaul Burton2013-11-09-0/+7
| | | | | | | | | | | | | | | | | | | | Malta boards may be used with cores which support L2 caches, however U-boot does not yet support L2 cache for MIPS. Thus for the moment we'll disable L2 caches by setting the L2B bit in Config2. This is specific to MTI/Imagination MIPS cores which is why this is done for the Malta board rather than generically. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: display "U-boot" on the LCD screenPaul Burton2013-11-09-0/+19
| | | | | | | | | | | | | | Displaying a message on the LCD screen is a simple yet effective way to show the user that the board has booted successfully. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: support for coreFPGA6 boardsPaul Burton2013-11-09-9/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: setup super I/O UARTsPaul Burton2013-11-09-0/+89
| | | | | | | | | | | | | | | | On a real Malta the Super I/O needs to be configured before we are able to access the UARTs. This patch performs that configuration, setting up the UARTs in the same way that YAMON would. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * qemu-malta: rename to just "malta"Paul Burton2013-11-09-1/+1
| | | | | | | | | | | | | | | | | | This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Merge branch 'iu-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-09-496/+936
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-07-3/+409
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| | * wandboard: README: Include the quad versionFabio Estevam2013-11-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Wandboard quad was not ported into U-boot at the time of writing the README. Add it to the list of Wandboard variants. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * i.MX6: nitrogen6x: fix erase size in 6x_upgrade.txtEric Nelson2013-10-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 6x_upgrade script is used to upgrade U-Boot in SPI-NOR on Nitrogen6x/SABRE Lite boards using U-Boot's 'sf' command. U-Boot is placed at offset 0x400 in flash, and the script currently only erases 0x50000 bytes. Since the current head is 319k, any additional features enabled in the configuration will exceed the space erased and cause errors re-programming the device. This patch increases the erase size to the full size of the region allocated for the U-Boot binary. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900Christoph G. Baumann2013-10-31-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn DRAM controller registers so the DRAM module will be correctly recognised. Signed-off-by: Christoph G. Baumann <c.baumann@ppc-ag.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | * ARM: mxs: Add PPC-AG BG0900 boardMarek Vasut2013-10-17-0/+257
| | | | | | | | | | | | | | | | | | | | | | | | This board supports FEC Ethernet, SPI NOR and NAND flash. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Christoph Baumann <c.baumann@ppc-ag.de>
| | * udoo: Add initial support for mx6q udoo boardFabio Estevam2013-10-17-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for mx6q udoo board. For further information about Udoo board: http://www.udoo.org/ Tested booting a mainline device tree kernel and a Yocto rootfs from mmc. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-05-0/+11
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